Metallization Airgap Structure to Cut Interconnect Capacitance
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Solution Overview
Problem
As IC devices miniaturize, the available area for forming contacts and interconnects becomes smaller, leading to increased routing complexity, parasitic resistance, and capacitance, which negatively impacts manufacturing cost and performance, and existing methods for forming airgaps in metal traces result in pinch-off issues that reduce process yield and reliability.
Innovation Solution
A semiconductor structure with metallization airgaps is created using a subtractive metal process, involving an adhesion layer, metal traces separated by uniform airgaps, and dielectric layers, where airgaps are formed by depositing and removing a sacrificial dielectric, ensuring consistent height and width without pinch-off, and using etch stop layers to maintain dielectric thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If airgaps are formed using existing methods, then interconnect capacitance is reduced, but pinch-off issues occur that reduce process yield and reliability
Solution Approach 1:
A sacrificial dielectric layer is deposited conformally over the metal traces and then selectively removed to form airgaps. This intermediary material enables controlled airgap formation without direct etching of the metal traces, eliminating pinch-off issues and improving process yield while achieving the desired capacitance reduction
Solution Approach 2:
The sacrificial dielectric layer is deposited conformally over the metal traces before airgap formation. This preliminary deposition ensures uniform coverage and protects the metal traces during subsequent processing steps, preventing pinch-off and ensuring reliable airgap formation with consistent dimensions
2Area of stationary object
If metal traces are miniaturized to reduce IC device size, then device area is reduced, but routing complexity and parasitic resistance increase
Solution Approach 1:
Dielectric material is selectively removed between adjacent metal traces to create airgaps, extracting the harmful parasitic capacitance while preserving the miniaturized trace layout. This reduces interconnect capacitance and allows for more efficient routing in miniaturized devices without increasing complexity
3Loss of energy
If airgap height is increased to reduce capacitance, then interconnect capacitance decreases, but dielectric thickness control becomes difficult
Solution Approach 1:
The sacrificial dielectric layer is deposited conformally to a predetermined thickness before airgap formation. This preliminary deposition with controlled thickness ensures that when the sacrificial material is removed, airgaps of precise and uniform height are formed, maintaining manufacturing precision while achieving capacitance reduction
Solution Approach 2:
The thickness of the sacrificial dielectric layer is precisely controlled during deposition to determine the final airgap height. By adjusting this parameter, the airgap dimensions are optimized to achieve the desired capacitance reduction while maintaining precise dielectric thickness control through the conformal deposition process
Data Source
AI summary
A semiconductor structure having metallization airgaps for subtractive metal processes and a method for making the same are disclosed. In an aspect, the semiconductor structure includes metal traces disposed above an adhesion layer and separated from each other in a horizontal direction by one or more airgaps having a height H. A dielectric layer is disposed above the metal traces but not above the airgaps. An etch stop layer (ESL) is disposed above the first dielectric layer and the airgaps. Each airgap extends from the top surface of the adhesion layer to the bottom surface of the first ESL and has a width that extends in the second horizontal direction from a side surface of the first metal trace, from a side surface of the second metal trace, or from the first metal trace to the second metal trace, depending on the pitch of the metal traces.