Metallization Structures Under Semiconductor Device Layer
Solution Overview
Problem
Current microelectronic device fabrication techniques lack effective methods for metallization under a semiconductor device layer, which is essential for 3D monolithic integration and high-density transistor arrays, as existing methods do not adequately address the need for metallization structures that can be routed close to the transistor fins while maintaining electrical and thermal conduction.
Innovation Solution
The development of metallization structures embedded within trenches and recesses formed between semiconductor fins, using conductive materials like copper, aluminum, or tungsten, which are self-aligned with the fin pattern and integrated into the dielectric layer to provide both electrical and thermal conduction paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metallization structures are formed under the semiconductor device layer, then electrical and thermal conduction paths are improved, but device structure complexity increases
Solution Approach 1:
The metallization structures are nested within the semiconductor device layer by forming trenches and recesses that extend into the device layer, allowing metal interconnects to be routed underneath active transistor regions while maintaining vertical integration. This nesting approach enables 3D monolithic integration by placing conductive paths in the vertical dimension rather than requiring additional lateral routing layers.
Solution Approach 2:
The patent transitions from traditional planar metallization to three-dimensional metallization by forming trenches and recesses that extend vertically into the semiconductor device layer. This dimensional change allows metallization structures to be positioned underneath transistors and other device components, enabling electrical and thermal conduction paths that were previously impossible in conventional two-dimensional layouts.
2Productivity
If metallization structures are routed close to transistor fins, then interconnect density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The methodology performs preliminary actions by first forming the semiconductor device structures (transistors, fins, gate stacks) and then using these structures as self-aligned references for subsequent trench formation and metallization deposition. The trenches are formed to extend alongside and underneath specific device regions, automatically positioning metallization structures with precise alignment to the fin pitch and device layout without requiring additional alignment steps.
Solution Approach 2:
The existing semiconductor device structures (transistor fins, gate stacks, isolation regions) serve as self-aligned masks and references for forming the metallization trenches. The device structures themselves define the positioning and geometry of the underlying metallization, eliminating the need for separate alignment processes and reducing manufacturing precision requirements while maximizing interconnect density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient electrical and thermal conduction paths under the semiconductor device layer, facilitating 3D integration and improving the performance of high-density transistor arrays by allowing metallization structures to be closely routed to the transistor fins without interfering with the gate stacks.
Implementation Method 1
metallization structures embedded within trenches and recesses formed between semiconductor fins, using conductive materials like copper, aluminum, or tungsten... to provide both electrical and thermal conduction paths
Implementation Method 2
metallization structures embedded within trenches and recesses formed between semiconductor fins, using conductive materials like copper, aluminum, or tungsten... to provide both electrical and thermal conduction paths
Data Source
AI summary
Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.