Multi-Finger-Channel Nanostructure for Transistor Current Crowding
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Solution Overview
Problem
Current semiconductor technologies face challenges in further shrinking the size and improving the performance of field-effect transistors, particularly in achieving balanced performance between NMOSFETs and PMOSFETs while reducing current crowding and leakage issues at high voltage operations.
Innovation Solution
The Multi-Finger-Channel Nanostructure (MFCNS) device design incorporates horizontal sheets physically connected by vertical fins, providing increased sidewall space for epitaxial growth and improved channel width, which reduces current crowding and enhances on-current performance, and allows for shared structures between input/output and core devices, enabling cost reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FinFET devices are used to shrink transistor size, then device dimensions are reduced, but current crowding and leakage issues worsen at high voltage operations
Solution Approach 1:
The channel region is divided into multiple segments: a first channel sheet, a second channel sheet, and vertical fins connecting them. This segmentation creates multiple current pathways that distribute current flow, reducing current crowding effects while maintaining compact device dimensions suitable for advanced technology nodes
Solution Approach 2:
The invention transitions from a planar 2D channel structure to a 3D multi-finger channel architecture by adding vertical fins that connect horizontal channel sheets. This dimensional evolution provides additional sidewall space for epitaxial growth and creates multiple current conduction paths, improving on-current performance and reducing leakage without further shrinking the device footprint
2Reliability
If NMOSFET and PMOSFET are designed with different structures to optimize individual performance, then device performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The MFCNS device structure serves as a universal architecture that can be configured for both NMOSFET and PMOSFET implementations. By adjusting doping types and gate materials while maintaining the same multi-finger channel geometry, the invention enables balanced performance optimization for both transistor types using a common manufacturing platform, reducing overall device complexity and manufacturing cost
Data Source
AI summary
A semiconductor device includes a channel region, a first source/drain region and a second source/drain region on opposing sides of the channel region, and a gate electrode over the channel region. The channel region includes a first portion having a first surface and a second surface opposite the first surface, a second portion having a third surface and a fourth surface opposite the third surface, such that the third surface of the second portion faces the second surface of the first portion, and a fin portion extending from the second surface of the first portion to the third surface of the second portion. The gate electrode surrounds at least a portion of the channel region.