3D Ferroelectric Layer Layout for MFM-MOSFET Memory Window
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Solution Overview
Problem
In ferroelectric random-access memory (FeRAM) cells with a planar design, the reduction in critical dimensions leads to a decrease in the size and variability of the orthorhombic-phase ferroelectric layer, resulting in a reduced memory window and reliability.
Innovation Solution
The ferroelectric layer is extended through multiple interconnect dielectric layers in both horizontal and vertical directions, increasing its length and area, thereby enhancing the presence of the orthorhombic-phase and improving the memory window and reliability of the MFM-MOSFET device without sacrificing device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimensions are reduced to increase device density, then device density is improved, but the size and variability of the orthorhombic-phase ferroelectric layer decreases, resulting in reduced memory window and reliability
Solution Approach 1:
The ferroelectric layer is extended from a planar two-dimensional structure into a three-dimensional structure by passing through multiple interconnect dielectric layers vertically. This dimensional transition allows the ferroelectric layer to achieve greater volume and area without increasing the horizontal critical dimensions, thereby maintaining high device density while improving memory window and reliability through increased orthorhombic-phase presence.
Solution Approach 2:
The ferroelectric layer is nested within multiple interconnect dielectric layers, with the layer extending through stacked dielectric structures. This nesting approach allows the ferroelectric layer to utilize the vertical space between dielectric layers, effectively increasing its volume and area while maintaining a compact horizontal footprint that preserves device density.
2Reliability
If the ferroelectric layer size is increased to improve memory window, then memory window is improved, but device density decreases
Solution Approach 1:
Instead of increasing the horizontal size of the ferroelectric layer, the invention extends it vertically through multiple interconnect dielectric layers. This allows the memory window to be improved through increased ferroelectric layer volume and orthorhombic-phase presence while maintaining small horizontal critical dimensions that preserve high device density.
Solution Approach 2:
The ferroelectric layer is configured with different regions having different orientations: a first region extending horizontally between source/drain regions and a second region extending vertically through interconnect dielectric layers. This local quality differentiation allows the vertical region to contribute to memory window improvement while the horizontal region maintains compact footprint for high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the memory window and reliability of the MFM-MOSFET device by increasing the instance of the orthorhombic phase in the ferroelectric layer, allowing for clearer discernment of data values and improved data storage capabilities.
Implementation Method 1
MFM-MOSFET devices are configured to store data values based on a process of reversible switching between polarization states because the ferroelectric layer's crystal structure is capable of changing when an electric field is present
Implementation Method 2
a negative voltage bias applied to the ferroelectric layer may induce atoms to shift into a first crystal structure orientation, which has a first resistance indicating a first data value
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion coupling the first lower horizontal portion to the first upper horizontal portion.