Micro-Bump Contact Testing via Daisy Chain Segmentation
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Solution Overview
Problem
Testing micro-bump contacts on integrated circuits (ICs) is challenging due to the large number of contacts, making it difficult to detect defects such as open and short circuits efficiently, which hinders the improvement of manufacturing processes.
Innovation Solution
Incorporating test circuits with daisy chain configurations and switching circuits that connect micro-bump contacts to form sets of daisy chains, allowing for the detection of short and open circuits, and determining their locations through binary search algorithms and segment bypassing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual micro-bump contacts are scanned one by one to detect defects, then measurement precision can be achieved, but testing time becomes excessively long (several hours)
Solution Approach 1:
The patent divides the array of micro-bump contacts into multiple groups, where each group is connected to a separate test pad. This segmentation allows parallel testing of multiple contacts simultaneously, reducing total testing time while maintaining the ability to precisely locate defects through systematic group-by-group analysis.
Solution Approach 2:
The patent merges multiple individual contact testing operations into parallel operations by connecting groups of contacts to shared test pads. This combining approach enables simultaneous testing of multiple micro-bump contacts, transforming a sequential process into a parallel process that significantly reduces testing time.
2Reliability
If a large array of micro-bump contacts is tested, then comprehensive defect detection is achieved, but device complexity increases
Solution Approach 1:
The patent designs test pads that serve multiple functions: each test pad connects to multiple micro-bump contacts through conductive traces, enabling a single test pad to perform multiple testing operations. This multi-functionality reduces the total number of test pads needed, simplifying the overall test circuit architecture while maintaining comprehensive defect detection coverage.
Solution Approach 2:
The patent transitions from a one-to-one mapping between test pads and contacts to a many-to-one mapping, organizing contacts in a grid pattern and connecting them through conductive traces to shared test pads. This dimensional reorganization reduces the number of test pads required while maintaining systematic coverage of all contacts.
3Adaptability or versatility
If the number of micro-bump contacts is increased to improve connectivity, then interconnection capability improves, but difficulty of detecting and measuring defects increases
Solution Approach 1:
The patent segments the large array of micro-bump contacts into smaller manageable groups, where each group is connected to a separate test pad. This segmentation maintains the high interconnection capability provided by the large contact array while simplifying defect detection by dividing the testing task into smaller, more manageable units that can be systematically analyzed.
Solution Approach 2:
The patent introduces conductive traces as intermediary elements that connect groups of micro-bump contacts to test pads. These traces serve as mediators that organize the complex interconnection structure into manageable sections, enabling systematic testing and defect location while preserving the high connectivity provided by the large contact array.
Data Source
AI summary
An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments (206, 208) in routing layers (1 16, 202) of the IC, and a plurality of micro-bump contacts (118, 204, 222) coupled to the routing circuitry. The IC includes a plurality of test circuits (102-104, 220, 302) coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first (230, 320) and second (232, 322) sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.