Micro-Display Substrate Layout for Uniform Common Electrode Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The development of silicon-based micro-displays faces challenges due to their high pixel density, leading to small sub-pixel sizes and tight pitch, which complicates the etching process and reduces uniformity, and the common electrode layer's flatness and electrical signal uniformity are compromised by the placement of conductive members.
Innovation Solution
An electronic device substrate design featuring a base substrate, insulating layer, light-emitting sub-units, and conductive members arranged in a specific configuration to improve the uniformity of the common electrode layer and etching process, including the use of annular conductive structures and strategic placement of conductive members to enhance electrical connections and reduce the risk of breakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high pixel density is used to achieve smaller sub-pixel sizes and tighter pitch, then resolution is improved, but etching uniformity deteriorates
Solution Approach 1:
The array region is divided into multiple etching regions separated by spacing structures. Each etching region contains a subset of sub-pixels and is processed independently during etching, allowing for better control and uniformity in each smaller region compared to processing the entire high-density array at once.
Solution Approach 2:
Spacing structures are introduced as intermediary elements between adjacent sub-pixel groups. These spacing structures act as physical separators that improve etching uniformity by preventing interference between adjacent etching regions while maintaining the high pixel density required for resolution.
2Reliability
If conductive members are placed in the periphery region surrounding the array region, then electrical connections are improved, but common electrode layer flatness deteriorates
Solution Approach 1:
The conductive members are extracted from the array region and relocated to the periphery region. This separation removes the disturbing effect of conductive members on the common electrode layer flatness in the display area, while still maintaining necessary electrical connections through the periphery placement.
Solution Approach 2:
Conductive members are arranged in an annular (ring-shaped) configuration in the periphery region, transitioning from a two-dimensional planar arrangement to a three-dimensional annular structure. This dimensional change allows electrical connections to be maintained while minimizing interference with the flatness of the common electrode layer in the array region.
3Reliability
If conductive members are placed close to the array region, then electrical signal uniformity is improved, but risk of breakage increases
Solution Approach 1:
Spacing structures are pre-formed between adjacent etching regions before the final conductive member formation. These pre-formed spacing structures provide mechanical support and stress relief, reducing the risk of breakage in conductive members while maintaining their proximity to the array region for electrical signal uniformity.
Solution Approach 2:
The conductive members are positioned asymmetrically in the periphery region with optimized spacing and orientation. This asymmetric arrangement allows electrical connections to be maintained close to the array region for signal uniformity, while the specific asymmetric positioning avoids high-stress areas and reduces breakage risk.
Data Source
AI summary
An electronic device substrate, a manufacturing method thereof, and an electronic device are provided. The electronic device substrate includes a base substrate, a first insulating layer, and light-emitting sub-units, a first conductive member and a second conductive member, which are on a side of the first insulating layer away from the base substrate. The light-emitting sub-units and the first conductive member are respectively in array region and periphery region, and the second conductive member is between the first conductive member and the array region; orthogonal projections of the first and second conductive members on the base substrate are spaced apart; each light-emitting sub-unit includes first and second driving electrodes, second driving electrodes of the light-emitting sub-units are integrated to form a first common electrode layer; the periphery region further includes a second common electrode layer electrically connected to the first conductive member and the first common electrode layer.