Micro LED Structure With Edge Conductivity Modulation
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Solution Overview
Problem
Reduced performance of optoelectronic devices due to higher leakage current, charge crowding, and unwanted recombination as device size decreases, particularly in vertical solid state devices like LEDs.
Innovation Solution
Manipulating lateral conduction in vertical solid state devices by modulating the n-doped layer conductivity and using MIS structures to bias the sidewalls, thereby redirecting current and balancing charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of optoelectronic devices is reduced to improve pixel density and cost, then device miniaturization is achieved, but device performance deteriorates due to higher leakage current, charge crowding, and unwanted recombination
Solution Approach 1:
The patent applies local quality by creating non-uniform doping concentrations within the device structure. Specifically, the doping concentration is varied laterally across the semiconductor layer, with higher doping near edges to suppress leakage current and lower doping in the center to maintain charge balance. This localized variation in doping quality allows the device to maintain high performance despite miniaturization.
Solution Approach 2:
The patent changes physical parameters by modulating the doping concentration profile and applying bias voltages to sidewall structures. The doping concentration is changed as a function of position, and electrical parameters are adjusted through biasing to dynamically control carrier distribution. These parameter changes enable the device to overcome the adverse effects of size reduction.
2Ease of manufacture
If uniform doping is used in vertical solid state devices, then manufacturing is simplified, but lateral current flow and charge imbalance occur at device edges
Solution Approach 1:
The patent replaces uniform doping with locally varied doping concentrations. The doping profile is specifically designed to have different concentrations at different lateral positions within the same vertical layer. This local quality variation suppresses edge-related harmful effects like leakage current while maintaining manufacturing feasibility through controlled doping processes.
3Productivity
If device size is reduced to increase pixel density, then more devices can be integrated on a substrate, but leakage current increases due to edge defects and surface states
Solution Approach 1:
The patent addresses leakage current by implementing local quality enhancement at device edges through higher doping concentrations and sidewall biasing structures. These localized modifications passivate surface states and reduce edge-related leakage, allowing miniaturized high-density pixel arrays to maintain low leakage current performance.
Solution Approach 2:
The patent introduces sidewall structures with biasing capabilities as intermediary elements between the active device region and the surrounding environment. These intermediary structures provide controlled electrical fields that repel minority carriers from edge regions, effectively reducing leakage current without affecting the core device functionality.
4Device complexity
If conventional lateral contact structures are used in miniaturized devices, then device fabrication is straightforward, but charge crowding occurs at interfaces and device performance degrades
Solution Approach 1:
The patent transitions from conventional two-dimensional lateral contacts to a three-dimensional contact architecture that includes vertical sidewall contacts. By utilizing the vertical dimension for contact formation, the patent reduces lateral current crowding at interfaces while maintaining electrical connectivity. This dimensional change allows for better charge distribution in miniaturized devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves device performance by reducing leakage current and enhancing charge balance, allowing for higher pixel density without patterning, thus addressing performance issues in miniaturized devices.
Implementation Method 1
the n-doped layer is modulated to have a lower conductivity towards an edge of the device
Implementation Method 2
a metal-insulator-semiconductor (MIS) structure is used to bias the sidewalls to reduce leakage current and balance charges
Data Source
AI summary
The present disclosure relates to a solid state micro device structure that has a microdevice formed on a substrate, with p and n doped layers, active layers between at least the two doped layers, pads coupled to each doped layer, and wherein the n-doped layer is modulated to have a lower conductivity towards an edge of the device. The invention further involves, dielectric layer, conductive layer, passivation layer and MIS structure.