Micro-LED Wafer Hybrid Bonding for 3 μm Pixel Pitch
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Solution Overview
Problem
Current micro-LED display technologies face challenges in achieving high resolution and efficiency due to integration issues between closely spaced III-V or III-N semiconductor LEDs and Si-CMOS ICs, leading to efficiency drops and difficulties in fabricating devices with small pixel pitches.
Innovation Solution
The method employs wafer-to-wafer hybrid bonding to integrate compound semiconductor LEDs or PDs with a CMOS IC, avoiding vias within the array and using a partial MESA etch to maintain a bottom contact size comparable to the quantum well area, allowing for high-resolution optical devices with minimal efficiency loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional integration methods are used to integrate closely spaced LEDs with CMOS IC, then integration is achieved, but efficiency drops due to non-radiative recombination at sidewalls
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by bonding the LED wafer to the CMOS IC wafer. This vertical integration allows closely spaced LEDs to be integrated with CMOS while maintaining LED efficiency, as the stacking approach minimizes sidewall exposure and non-radiative recombination compared to lateral integration methods.
Solution Approach 2:
The patent divides the integration process into separate wafer-level processing steps: LED array fabrication on a first wafer, CMOS IC fabrication on a second wafer, and subsequent bonding. This segmentation allows each component to be optimized independently before integration, preserving LED efficiency while achieving the required integration density.
2Manufacturing precision
If LED pixel pitch is reduced to achieve high resolution, then resolution improves, but efficiency drops due to increased perimeter to area ratio
Solution Approach 1:
By implementing vertical stacking of LED and CMOS wafers, the patent enables reduced LED pixel pitch in the horizontal plane without proportionally increasing the perimeter-to-area ratio that causes efficiency loss. The three-dimensional configuration allows high-resolution pixel arrays while maintaining larger effective light-emitting areas compared to planar designs.
3Manufacturing precision
If wafer-to-wafer hybrid bonding is used to integrate LEDs with CMOS IC, then high resolution with small pixel pitch is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct phases: LED wafer processing, CMOS wafer processing, and final bonding. This segmentation allows each phase to be optimized independently using standard manufacturing techniques, reducing overall process complexity despite the advanced integration achieved through wafer-to-wafer hybrid bonding.
Data Source
AI summary
An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (μLED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.