Conductive Micro Via Array for 3D Fo-WLCSP Vertical Interconnects
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Solution Overview
Problem
Conventional three-dimensional (3-D) fan-out wafer level chip scale packages (Fo-WLCSPs) face challenges in forming reliable and cost-effective vertical electrical interconnects due to issues with redistribution layers (RDLs) such as cracking, warping, and poor connectivity, which increase fabrication costs and lead to defects.
Innovation Solution
A method involving the formation of a conductive micro via array outside the semiconductor die's footprint, with through-mold-holes (TMHs) created to expose the micro via array, providing a robust and efficient vertical interconnect structure that enhances electrical and mechanical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple redistribution layers (RDLs) are formed over front side and backside of semiconductor die to accomplish electrical interconnection for 3-D device integration, then vertical electrical interconnection is achieved, but the fabrication process becomes slow and costly
Solution Approach 1:
The patent forms the array of conductive micro vias and fills them with conductive material before forming the RDL traces. This preliminary action allows subsequent RDL formation to be a simple deposition process rather than requiring complex multi-step patterning and etching, significantly reducing fabrication time and cost while achieving the same electrical interconnection function.
Solution Approach 2:
The patent uses the TMH array as a mold or template to create uniformly spaced conductive micro vias. This copying approach ensures precise alignment and spacing of interconnect structures without requiring complex lithography alignment processes, speeding up fabrication while maintaining high precision.
2Reliability
If conductive interconnect structures are formed within Fo-WLCSPs to provide vertical electrical interconnection, then electrical connectivity is improved, but the process reduces structural support for redistribution layers particularly when openings are formed in the package
Solution Approach 1:
The patent introduces a dielectric material as an intermediary substance that fills the TMHs alongside or instead of conductive material. This dielectric intermediary provides structural support to the RDLs while the conductive micro vias provide electrical connection, separating the structural and electrical functions to eliminate the trade-off between connectivity and support.
Data Source
AI summary
A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array.