Micro Via PCB Design Reducing Parasitic Effects
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Solution Overview
Problem
Dual-sided high-speed connector designs in printed circuit boards (PCBs) suffer from bandwidth degradation due to parasitics associated with stacked or through-hole vias, limiting signal transmission to data rates of about 14 gigabits per second or less.
Innovation Solution
The formation of micro vias in PCBs with diameters less than or equal to 100 microns, using a through hole with an electrically conductive pillar and backfilling with epoxy to reduce parasitic capacitance and impedance, allowing for higher data transmission rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked or through hole vias are used in dual-sided high-speed connector designs, then structural connectivity is achieved, but parasitic effects increase causing bandwidth degradation and limiting signal transmission to 14 Gbps or less
Solution Approach 1:
The via structure is segmented into multiple components: a through hole in the PCB substrate, an electrically conductive pillar positioned within the hole, and epoxy backfill material surrounding the pillar. This segmentation allows each component to be optimized independently - the pillar provides conductivity while the epoxy reduces parasitic capacitance, resolving the contradiction between connectivity and parasitic reduction
Solution Approach 2:
The micro via employs composite materials by combining an electrically conductive pillar (such as copper or other conductive material) with epoxy backfill material. This composite structure enables the via to simultaneously provide electrical connectivity through the conductive pillar while reducing parasitic effects through the epoxy material, directly addressing the technical contradiction
2Ease of manufacture
If conventional via designs are used, then manufacturing simplicity is maintained, but high-frequency performance above 10 GHz deteriorates with more than 1 dB loss
Solution Approach 1:
The through hole is formed and prepared in advance in the PCB substrate before the pillar is positioned and epoxy is backfilled. This preliminary action simplifies the manufacturing process by establishing the basic structure first, then adding the functional components (pillar and epoxy) in subsequent steps, maintaining ease of manufacture while achieving high-frequency performance
Solution Approach 2:
The epoxy backfill is applied locally around the pillar within the through hole, providing parasitic reduction specifically where needed in the via structure. This localized application maintains manufacturing simplicity by targeting only the critical region while achieving the required high-frequency performance improvement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signal transmission performance by reducing parasitic effects, enabling data rates beyond 14 gigabits per second and improving the density and area utilization of PCBs in high-speed applications.
Implementation Method 1
Signal transmission in such designs may be degraded due to parasitics associated with stacked or through hole vias
Data Source
AI summary
Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill.