Uniform Microcell Library for Parallel Subword VLSI Logic
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Solution Overview
Problem
Existing semiconductor designs face challenges in exploiting parallelism due to data-flow dependencies, leading to suboptimal processing throughput and resource utilization in application-specific integrated circuits (ASICs).
Innovation Solution
A microcell library comprising microcells with uniform input and output operands, capable of performing partial arithmetic and logic operations, is introduced to enhance parallelism and efficiency by allowing operations on sub-atomic data fragments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard-cell methodology is used to design ASICs, then design complexity is reduced and manufacturing is simplified, but processing throughput is limited due to data-flow dependencies preventing effective parallelism exploitation
Solution Approach 1:
The patent segments standard logic gates into finer-grained microcells with uniform 3-input 2-output interfaces. Each microcell performs a specific computational function (arithmetic, logic, shift, or control-flow operations) on sub-atomic data fragments. This segmentation enables independent operation of microcells, allowing parallel execution despite data-flow dependencies in the overall computational logic, thereby improving processing throughput while maintaining manageable design complexity through standardized microcell interfaces
Solution Approach 2:
The patent introduces a new dimension of parallelism by operating on sub-atomic data fragments (subwords) rather than complete data words. By breaking down data into smaller sub-atomic units and processing them through multiple microcells simultaneously, the architecture exploits parallelism at a finer granularity level, overcoming the limitation of data-flow dependencies that constrain parallelism at the data-word boundary level
2Speed
If data width is reduced to operate faster and consume fewer resources, then processing speed increases and area consumption decreases, but precision and computational accuracy are compromised
Solution Approach 1:
The patent applies partial action by having microcells operate on sub-atomic data fragments (partial data words) rather than complete data words. Each microcell processes a portion of the data (e.g., 2-bit, 4-bit, or 8-bit subwords) independently and simultaneously. This partial processing approach enables faster computation with reduced area consumption while maintaining full data precision through parallel processing of multiple sub-atomic fragments that collectively represent the complete data word
3Productivity
If microcells operate on sub-atomic data fragments with uniform interface, then parallelism is enhanced and processing throughput increases, but device complexity and interconnection requirements increase
Solution Approach 1:
The patent implements universality by designing all microcells with a standardized 3-input 2-output interface regardless of their specific computational function. This uniform interface allows any microcell to be connected to any other microcell in a regular grid-like architecture, simplifying interconnection requirements. The standardized interface enables flexible configuration of microcells to implement different computational logic while maintaining simple and systematic interconnection patterns, thus enhancing parallelism without proportionally increasing interconnection complexity
Data Source
AI summary
A microcell library including a plurality of microcells is provided for implementing subscalar digital arithmetic computing paradigm. Each of the plurality of microcells may implement a primitive logic and has a uniform interface with three input operands at an input interface and two output operands at an output interface. The two output operands in a clock cycle are latched to one or more output registers. Each microcell is configured to perform one of a partial arithmetic operation based on the three input operands to generate the two output operands, or a logical operation based on at least two of the three input operands to generate at least one of the two output operands. Each of the three input operands and each of the two output operands have a uniform pre-defined valency.