Microdevice Array Bonding Using Planarization Layers

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Solution Overview

Problem

There is a challenge in conducting a reliable and selective transfer and bonding of micro devices to a backplane, particularly in optoelectronic solid-state array devices, where existing methods lack efficiency and reliability.

Innovation Solution

The method involves forming bumps on micro devices and a backplane, using a planarization layer to align and bond them, and curing the adhesive layer to create a stable connection, which can include applying pressure, temperature, light, or microwave exposure to fuse the adhesive layers, ensuring mechanical and electrical stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional bonding methods are used to transfer micro devices to backplane, then the process can be completed, but the reliability and efficiency of bonding is insufficient

Engineering Contradiction:
Improvebonding reliabilityVSAvoidbonding efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces a planarization layer as an intermediary substance between the micro device bumps and the backplane. This layer fills the gaps and non-uniformities in the bump array, providing a flat bonding surface that improves both bonding reliability and efficiency. The planarization layer acts as a mediator that enables reliable electrical and mechanical contact while accommodating variations in bump heights and spacing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If bumps are formed on micro devices and backplane for bonding, then electrical contact is achieved, but surface profile non-uniformity causes alignment and bonding difficulties

Engineering Contradiction:
Improveelectrical contact reliabilityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies planarization treatment to the bump array before the actual bonding process. By filling the gaps and non-uniformities in advance, the planarization layer creates a flat surface that facilitates precise alignment between the micro device array and the backplane. This preliminary action eliminates alignment difficulties caused by surface irregularities while preserving the electrical contact function of the bumps.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If planarization layer is applied to fill spaces between micro devices and bumps, then alignment is improved, but additional processing steps are required

Engineering Contradiction:
Improvealignment precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The planarization layer serves multiple functions simultaneously: it fills the gaps between bumps, provides a flat bonding surface for alignment, enables reliable electrical contact, and accommodates variations in bump heights. By combining these functions into a single layer and processing step, the patent achieves improved alignment precision without proportionally increasing process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables a reliable and efficient bonding process that provides mechanical stability and electrical contact between micro devices and the backplane, accommodating surface profile non-uniformity and ensuring durable connections.

Implementation Method 1

curing the at least one planarization layer

Methodology Applied
Scientific EffectCuring: Photopolymerisation

Implementation Method 2

curing the adhesive layer to create a stable connection, which can include applying pressure, temperature, light, or microwave exposure to fuse the adhesive layers

Methodology Applied
Scientific EffectMicrowave heating: Dielectric Heating

Data Source

PatentUS20240413134A1Optoelectronic solid state array
Publication Date: 2024.12.12 VUEREAL INC
  • US20240413134A1 patent drawing
  • US20240413134A1 patent drawing
  • US20240413134A1 patent drawing

AI summary

Structures and methods are disclosed for fabricating optoelectronic solid state array devices. In one case a backplane and array of micro devices is aligned and connected through bumps.