Microelectronic Base Structure for 3D Memory Array Integration
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Solution Overview
Problem
The complexity and density of microelectronic device memory arrays hinder the formation of efficient conductive contacts and impede reductions in size and performance improvements, such as faster memory cell switching and lower power consumption, due to processing limitations and the complexity of control logic devices.
Innovation Solution
A method of forming a microelectronic device structure with a base structure that includes a semiconductive or glass material, where a source material is formed around the periphery and laterally removed to expose an etch stop material, allowing for the growth of epitaxial material and the formation of memory arrays and interconnects, facilitating improved fabrication and protection of components during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical memory array architectures are used to increase memory density, then the number of memory cells per unit area increases, but the complexity of control logic devices and difficulty of forming conductive contacts increase
Solution Approach 1:
The patent divides the memory device into separate structures: a memory array structure and a control logic structure. The memory array is formed on a first substrate while control logic devices are formed on a second substrate, then the structures are bonded together. This segmentation allows independent optimization of each component and simplifies the overall system complexity.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional integration by stacking the memory array structure and control logic structure vertically. This allows high-density memory arrays to be combined with control logic without increasing lateral footprint, thereby increasing memory density while maintaining manageable control logic complexity.
2Manufacturing precision
If processing conditions are optimized for memory array formation, then memory array quality improves, but control logic device configurations and performance are limited
Solution Approach 1:
By separating the memory array and control logic into different structures formed on different substrates, each can be processed under its own optimal conditions. The memory array can undergo high-temperature processing for quality formation, while the control logic on the separate substrate maintains its performance characteristics without being constrained by the memory array's processing requirements.
3Area of stationary object
If the horizontal footprint of the memory device is reduced, then device size decreases, but the quantities and dimensions of control logic devices are compromised
Solution Approach 1:
The patent employs three-dimensional stacking to bond the memory array structure with the control logic structure vertically. This allows the device to maintain a small horizontal footprint while accommodating both high-density memory arrays and adequate control logic components in the vertical dimension, effectively decoupling device size from control logic arrangement complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of compact, high-performance microelectronic devices with improved memory cell switching speed and reduced power consumption by simplifying the fabrication process and protecting sensitive components during backside processing.
Implementation Method 1
The base structure may be formed to facilitate removal of the base structure from the first microelectronic device structure after attachment of the first microelectronic device structure to the second microelectronic device structure. In some embodiments, the base structure includes one or more etch stop materials that may facilitate protection of other components of the first microelectronic device structure during removal of the base material.
Implementation Method 2
epitaxial material grown from the doped semiconductive material to fill the openings and cover the dielectric material
Data Source
AI summary
A method of forming a microelectronic device comprises forming a source material around substantially an entire periphery of a base material, and removing the source material from lateral sides of the base material while maintaining the source material over an upper surface and a lower surface of the base material. Related methods and base structures for microelectronic devices are also described.