Microelectronic Assembly Co-Support System
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Solution Overview
Problem
Conventional microelectronic packages occupy a larger area than necessary due to the extensive space required for electrical connections, which is a challenge in compacting multiple chips for portable devices and other applications where size reduction is crucial.
Innovation Solution
A microelectronic assembly system with a set of terminals and a microelectronic element having a memory storage array, where the contacts are configured to receive command and address information according to different predetermined arrangements for different types of microelectronic assemblies, allowing for efficient sampling and reduced physical size through package-on-package stacking and shared conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional microelectronic packages use extensive electrical connections with terminals placed in sets of columns adjacent to peripheral edges, then reliable electrical connectivity is achieved, but the package occupies a larger area than necessary
Solution Approach 1:
The patent transitions from a two-dimensional arrangement of terminals at peripheral edges to a three-dimensional stacked configuration where microelectronic assemblies are vertically stacked and interconnected. This vertical stacking reduces the footprint area while maintaining all necessary electrical connections through inter-layer vias and conductors.
Solution Approach 2:
The patent implements package-on-package stacking where one microelectronic assembly is placed on top of another, with lower assemblies nested beneath upper assemblies. This nesting approach allows multiple functional layers to occupy the same horizontal footprint, effectively reducing the overall package area while preserving all electrical connectivity requirements.
2Area of stationary object
If multiple chips are packed into a small space for portable devices, then size reduction is achieved, but the complexity of interconnecting I/Os increases
Solution Approach 1:
The patent creates a universal interconnection architecture where a single set of conductors and contacts serves multiple functions across different stacked assemblies. The same physical infrastructure supports I/O interconnections for multiple chips, eliminating the need for separate dedicated interconnection paths for each chip pair and thereby reducing overall complexity.
Solution Approach 2:
The patent merges multiple I/O interconnection functions into a unified stacked assembly structure. By combining multiple chips and their interconnections into a single vertical package, the patent reduces the number of separate interconnection systems needed, simplifying the overall design while achieving compact size.
3Area of stationary object
If terminals are placed in sets of columns at peripheral edges for conventional packages, then ease of connection to circuit panels is achieved, but the package area increases significantly
Solution Approach 1:
The patent moves connection points from the two-dimensional peripheral edges to a three-dimensional stacked configuration with vertical interconnections. This allows connection points to be distributed across multiple vertical levels while maintaining ease of connection to circuit panels through the stacked assembly's external terminals.
Solution Approach 2:
The patent pre-configures the stacked assembly with all necessary internal interconnections and vertical conductors before final attachment to the circuit panel. This preliminary arrangement of connections within the stacked package simplifies the final installation process, as the entire multi-chip assembly connects to the panel as a single unit rather than requiring individual chip connections.
Data Source
AI summary
A system includes a microelectronic assembly having terminals and a microelectronic element, and a component for connection with the microelectronic assembly. The component includes a support structure bearing conductors configured to carry command and address information, and contacts coupled to the conductors and connected with the terminals of the microelectronic assembly. The contacts have address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.