Multilevel Microelectronic Structure via Stress-Induced Folding
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Solution Overview
Problem
The production of three-dimensional microelectronic structures faces challenges in creating active components like MOS transistors at higher levels without degrading existing components, as high temperatures required for some steps exceed the thermal budget of sensitive components, such as source and drain electrodes, and result in poor quality gate oxides and epitaxial layers.
Innovation Solution
A method involving the formation of a first layer as a sacrificial layer to generate mechanical stress in a second layer, allowing the second layer to move and fold upon stress relaxation, enabling the assembly of microelectronic patterns without impacting the thermal budget of lower levels, thus allowing for the production of active components like MOS transistors at higher levels with improved quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperatures are used to produce active components at higher levels, then the quality of gate oxides and epitaxial layers is improved, but the previously produced components are degraded due to exceeding their thermal budget
Solution Approach 1:
The fabrication process is segmented into separate thermal zones: the first level is fabricated first and then protected from subsequent high-temperature processing. The second level is fabricated independently after the first level is complete, allowing each level to have its own optimized thermal budget. This segmentation enables high-quality gate oxides and epitaxial layers at the second level without degrading the first level components.
Solution Approach 2:
The first level is completely fabricated and protected before beginning fabrication of the second level. All necessary components, interconnects, and protective layers are prepared in advance on the first level. This preliminary action allows the second level to be processed at high temperatures required for quality gate oxides and epitaxial layers without exposing the first level to degrading thermal conditions.
2Object-affected harmful factors
If low temperatures are used to protect previously produced components, then thermal degradation is avoided, but the quality of gate oxides and epitaxial layers deteriorates
Solution Approach 1:
The fabrication process is divided into sequential stages where the first level is completed and protected before second level fabrication begins. This segmentation allows the second level to undergo high-temperature processing for quality gate oxides and epitaxial layers without exposing the first level to such conditions, thus avoiding thermal degradation while maintaining manufacturing precision.
Solution Approach 2:
The first level is fully fabricated and protected in advance before second level processing. This preliminary action creates a thermal barrier that protects the first level from subsequent high-temperature processing, enabling the second level to achieve high-quality gate oxides and epitaxial layers at temperatures exceeding 400°C without compromising the first level components.
3Productivity
If successive levels are produced on the same substrate, then integration density is increased, but thermal management becomes difficult due to cumulative thermal budgets
Solution Approach 1:
The substrate is segmented into separate fabrication zones for different levels. The first level is fabricated in one zone and then protected, while the second level is fabricated in another zone with independent thermal control. This segmentation allows each level to have its own optimized thermal budget, enabling high integration density without cumulative thermal constraints affecting overall process quality.
Solution Approach 2:
The first level is completely fabricated and protected before second level fabrication begins. This preliminary action establishes a thermal barrier that decouples the thermal budgets of different levels. The second level can then be processed at high temperatures required for quality gate oxides and epitaxial layers without the thermal constraints that would otherwise limit successive level fabrication on the same substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the production of high-quality active components across multiple levels without thermal degradation, enabling efficient assembly and integration of microelectronic structures while maintaining the integrity of previously formed components.
Implementation Method 1
The second layer is formed so as to generate a mechanical stress in it
Implementation Method 2
allowing relaxation of at least part of said stress
Data Source
AI summary
A method for producing a multilevel microelectronic structure includes formation of a first layer, production of at least one second layer at least partially covering the first layer, and production of at least one microelectronic pattern on or in the second layer. The second layer is formed so as to generate a mechanical stress in it, the first layer forms, for the second layer, a support preventing relaxation of the stress. After the production of at least one microelectronic pattern, the method includes at least elimination of at least part of the first layer, thus making it possible to relax at least part of the mechanical stress on the second layer so that at least a portion of the second layer covering the eliminated part of the first layer moves, and fixing the moved portion of the second layer to a structure part that has remained fixed.