Micro-Structured Thin Film Capacitors for Low-Latency Substrates
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Solution Overview
Problem
Conventional IC packages face challenges in meeting capacitance demands due to limitations in integrating capacitors, such as increased latency, occupied surface area, and z-height, with existing solutions like MIM capacitors and package substrates leading to inefficient power delivery and long electrical pathways.
Innovation Solution
Incorporation of micro-structured capacitors (MSCs) in situ within the substrate, utilizing a high-k dielectric layer between vertically interlocked conductive layers, fabricated using a lithography process on a glass carrier, allowing for higher annealing temperatures without affecting electronic circuitry and enhancing capacitor surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MIM capacitors are integrated into the die, then capacitance is provided, but latency increases and surface area is occupied
Solution Approach 1:
The patent transitions capacitor integration from the planar die surface to the vertical substrate dimension. By fabricating thin film capacitors within the substrate layers rather than on the die surface, the solution eliminates the latency associated with MIM capacitors while providing capacitance in a different spatial dimension that does not occupy valuable die surface area.
Solution Approach 2:
The patent extracts the capacitor fabrication process from the die itself and relocates it to the substrate. By taking out the capacitor integration from the die structure and implementing it in the substrate using thin film deposition techniques, the solution resolves the latency issue while maintaining capacitance functionality.
2Quantity of substance
If capacitors are placed on package substrate, then capacitance is provided, but electrical pathway length increases
Solution Approach 1:
The patent merges the capacitor structure with the substrate itself by fabricating thin film capacitors directly within the substrate layers. This integration eliminates the need for separate package substrate capacitors and their associated long electrical pathways, as the capacitors become an inherent part of the substrate structure through which signals travel minimal distances.
3Quantity of substance
If high annealing temperatures are used for inorganic dielectric materials, then high dielectric constant is achieved, but compatibility with electronic circuitry is reduced
Solution Approach 1:
The patent changes the material parameter from high-temperature inorganic dielectric materials to low-temperature organic dielectric materials. This parameter change allows the use of lower annealing temperatures that are compatible with existing electronic circuitry while still achieving the required dielectric properties for capacitor functionality.
Solution Approach 2:
The patent employs composite material strategies by using organic dielectric materials that can be processed at lower temperatures alongside standard semiconductor materials. This composite approach enables process compatibility across different material systems without requiring high-temperature annealing that would damage sensitive electronic circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MSCs provide improved power efficiency and design flexibility by positioning capacitors closer to the die, reducing latency and eliminating the need for stacked vias, while using materials that can withstand higher annealing temperatures.
Implementation Method 1
a high-k dielectric material between the first microstructures and the second microstructures
Implementation Method 2
fabricated using a lithography process on a glass carrier
Implementation Method 3
allowing for higher annealing temperatures without affecting electronic circuitry
Data Source
AI summary
Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic substrate with an in situ capacitor, the capacitor may include a first conductive layer having first microstructures at a first surface, a second conductive layer on the first conductive layer and having second microstructures at a second surface, where the second microstructures vertically interlock with the first microstructures, and a high-k dielectric material between the first microstructures and the second microstructures.