Mid-Die SERDES Packaging Architecture for Low-Latency Die Links
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Solution Overview
Problem
Existing integrated circuit (IC) packaging technologies face challenges with increased latency and interconnect density due to multiple hops in communication pathways between IC dies, particularly in large compute arrays, which are not effectively addressed by current interconnect technologies using solder or equivalent materials.
Innovation Solution
A quasi-monolithic hierarchical integration architecture using recursively coupled IC dies with sub-10 micrometer pitch die-to-die interconnects and through-dielectric vias to reduce effective interconnection area and latency, employing hybrid bonds and conductive pathways between SERDES circuits across non-coplanar layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple hops are used in 2.5D and 3D packaging architectures, then connectivity between dies is achieved, but latency increases
Solution Approach 1:
The system segments the monolithic die into multiple smaller dies that are packaged separately and then interconnected through a package substrate. This segmentation allows each die to be optimized independently while maintaining overall system functionality, resolving the contradiction by enabling connectivity without requiring a single large die that would incur high latency.
Solution Approach 2:
A package substrate acts as an intermediary component that connects multiple dies through controlled impedance traces. This intermediary enables signal transmission between dies while allowing optimization of trace lengths and routing to minimize latency, thus achieving connectivity without the latency penalty of direct monolithic integration.
2Loss of time
If die size is increased to reduce interconnect hops, then latency is reduced, but interconnect density limitations are encountered
Solution Approach 1:
The system transitions from planar interconnection to three-dimensional stacking architecture, where dies are arranged in multiple layers and connected through vertical interconnect access (via) holes and through-silicon vias (TSVs). This dimensional change enables high interconnect density by utilizing the vertical dimension, allowing numerous connections without increasing lateral die size or complexity.
3Reliability
If vertical and horizontal interconnect density is increased, then more connections are achieved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: individual die fabrication, separate packaging of each die, and subsequent assembly on the package substrate. This segmentation allows each stage to be optimized independently using existing manufacturing capabilities, avoiding the need for a single complex monolithic fabrication process that would be required to achieve high interconnect density in a traditional approach.
4Device complexity
If monolithic die is used, then integration is simplified, but yield is reduced due to entire die discard requirement
Solution Approach 1:
The monolithic die is segmented into multiple smaller dies that can be independently fabricated and packaged. This segmentation enables independent yield management for each die, so that defects in one die do not necessitate discarding the entire wafer or large portions of it. Each die can be tested and packaged separately, improving overall yield while maintaining integration through the package substrate interconnection.
Data Source
AI summary
A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die having a first connection to a first serializer/deserializer (SERDES) circuit and a second connection to a second SERDES circuit; a second IC die having the first SERDES circuit; and a third IC die having the second SERDES circuit, in which the first IC die is in a first layer, the second IC die and the third IC die are in a second layer not coplanar with the first layer, the first layer and the second layer are coupled by interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and the first SERDES circuit and the second SERDES circuit are coupled by a conductive pathway.