Miller Plateau Sampling Circuit for Power Transistor Gate Monitoring
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Solution Overview
Problem
Measuring the Miller plateau voltage of a power transistor is challenging due to its very short duration, making it difficult to obtain valuable information on current conduction through the Field Effect Transistor (FET).
Innovation Solution
A method and apparatus for automatic sampling of the Miller plateau voltage using feedback from a switching event, involving a sampling transistor and capacitor to precisely measure the voltage under tight timing constraints, adapting to environmental changes, and utilizing an Analog to Digital Converter (ADC) or analog comparators to quantify the sampled voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional measurement methods are used to measure Miller plateau voltage, then the measurement system is simple, but the measurement precision is poor due to the very short duration of the Miller plateau voltage
Solution Approach 1:
The sampling transistor and capacitor are pre-configured and ready before the Miller plateau event occurs. The sampling circuit is designed to automatically capture the voltage when the plateau occurs, rather than requiring continuous monitoring or post-event analysis. This preliminary preparation enables precise measurement of the fleeting Miller plateau voltage without requiring complex continuous measurement systems.
Solution Approach 2:
A sampling capacitor is introduced as an intermediary element to capture and hold the Miller plateau voltage. The capacitor acts as a temporary storage medium that freezes the voltage value during the brief plateau period, allowing subsequent measurement without requiring the measurement instrument to operate at extremely high speeds. This intermediary approach simplifies the measurement system while improving precision.
2Measurement precision
If continuous monitoring is used to capture the Miller plateau voltage, then the measurement precision improves, but the loss of time increases due to the continuous operation required
Solution Approach 1:
Instead of continuous monitoring, the sampling circuit operates periodically or event-triggered. The sampling transistor is activated only when the Miller plateau condition is detected, allowing the circuit to remain in a low-power standby state otherwise. This periodic operation captures the necessary measurement data without the time penalty of continuous monitoring, reducing both measurement time and power consumption while maintaining precision.
Solution Approach 2:
The sampling circuit is designed to rapidly capture the Miller plateau voltage in a single fast operation rather than through prolonged continuous measurement. The sampling transistor quickly charges the capacitor during the brief plateau period, then immediately holds the value for measurement. This rushing through the critical measurement window minimizes the time required while ensuring accurate capture of the voltage value.
3Device complexity
If a simple voltage divider is used to measure the Miller plateau voltage, then the device complexity is low, but the measurement precision is insufficient under tight timing constraints
Solution Approach 1:
The sampling capacitor serves as an intermediary that decouples the timing-critical sampling operation from the measurement operation. By capturing the voltage on the capacitor during the brief Miller plateau, the circuit allows subsequent measurement without tight timing constraints. This approach maintains relatively simple circuitry while achieving high measurement precision by separating the sampling and measurement functions in time.
Solution Approach 2:
The sampling transistor and capacitor are pre-configured to automatically capture the voltage when the Miller plateau occurs, eliminating the need for complex real-time measurement circuits. The preliminary setup of the sampling circuit allows it to instinctively capture the voltage value without requiring complex control logic or high-speed measurement instrumentation, thus maintaining simplicity while improving precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable measurement of the Miller plateau voltage, providing useful information on current conduction through the FET, facilitating safety and redundancy applications, and detecting faults or short circuits by determining the conducted current.
Implementation Method 1
A sampling capacitor is connected between a second source and a ground, wherein the second transistor is configured to sample a Miller plateau voltage of the first gate voltage on the sampling capacitor
Data Source
AI summary
A system includes a power transistor having a first drain connected to a load, a first gate connected to a gate driver, wherein the gate driver is configured to drive a first gate voltage on the first gate, and a first source connected to a ground. A sampling transistor includes a second drain connected to the first gate, a second gate connected to the first drain and a second source. A sampling capacitor is connected between the second source and the ground, wherein the sampling transistor is configured to sample a Miller plateau voltage of the first gate voltage on the sampling capacitor, in response to the first gate voltage increasing to the Miller plateau voltage and a first drain voltage of the first drain decreasing to a value equal to the Miller plateau voltage plus a threshold voltage of the sampling transistor.