MIM Capacitor 3D Sidewall Electrodes for High Density
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Solution Overview
Problem
Current methods for fabricating metal-insulator-metal (MIM) capacitors in semiconductor device fabrication face challenges in improving capacitance and structural integration within the BEOL interconnect structure, particularly in achieving efficient electrode and dielectric layer integration.
Innovation Solution
The method involves depositing an interlayer dielectric layer with apertures, forming a layer stack comprising a bottom electrode, capacitor dielectric, and top electrode, and using a block mask to define the perimeter of the layer stack, which increases the effective plate area of the MIM capacitor, enhancing capacitance while maintaining a compact footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MIM capacitor fabrication methods are used, then the fabrication process is simpler, but the capacitance density is lower and surface area requirements are higher
Solution Approach 1:
The patent transitions from planar capacitor electrodes to three-dimensional electrodes that extend vertically along aperture sidewalls. The layer stack is deposited conformally on the sidewalls of apertures formed in the interlayer dielectric, creating vertical capacitor structures that utilize the third dimension (height) to increase capacitance without proportionally increasing footprint area.
Solution Approach 2:
The capacitor structure is nested within the BEOL interconnect architecture. Apertures are formed in existing interlayer dielectric layers, and the capacitor layer stack is deposited within these apertures and on their sidewalls, nesting the capacitor structure within the established interconnect framework rather than requiring separate dedicated areas.
2Manufacturing precision
If critical masks are used to define capacitor perimeters, then manufacturing precision is higher, but device complexity and fabrication difficulty increase
Solution Approach 1:
A block mask is introduced as an intermediary element to define the perimeter of the capacitor structure. The block mask is deposited as a conformal layer that is subsequently anisotropically etched to create vertical sidewalls, serving as a mediator that simplifies the overall patterning process compared to using multiple critical alignment masks.
Solution Approach 2:
Instead of using positive lithography masks to directly pattern the capacitor electrodes, the patent uses a block mask that is deposited conformally and then anisotropically etched. This inverts the conventional approach by using deposition and directional etching rather than lithographic patterning to define the capacitor geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases capacitance density, reduces surface area requirements, improves capacitor reliability, and simplifies the integration process by replacing critical masks with a non-critical block mask, resulting in a 50% areal reduction for equivalent capacitance values compared to conventional structures.
Implementation Method 1
depositing an interlayer dielectric (ILD) layer
Implementation Method 2
A layer stack, which includes a bottom electrode layer and a capacitor dielectric layer, is deposited on the top surface of the ILD layer and the sidewalls bounding each of the apertures
Data Source
AI summary
Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.