MIM Capacitor Pad Design for Via Isolation

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Solution Overview

Problem

In semiconductor devices, the integration of capacitors and vias leads to substrate expansion and potential deformation of dielectric layers, which lowers the breakdown voltage of capacitors, especially when capacitors are arranged alongside vias or overlap with them.

Innovation Solution

A semiconductor device design where a first insulating film is sandwiched between the pad and the lower electrode of the capacitor, with the pad covering the via and being electrically connected to the via metal, effectively preventing substrate expansion and deformation by using a stiff insulating material like silicon oxide to reinforce the pad and maintain capacitor integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the capacitor and via are arranged side by side, then the electrical connectivity is ensured, but the substrate size expands

Engineering Contradiction:
Improveelectrical connectivityVSAvoidsubstrate size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention merges the capacitor and via structures by allowing the pad to fully cover the via, with the via passing through the pad to the back surface of the substrate. This vertical integration enables electrical connectivity while reducing planar footprint, as the capacitor overlaps with the via structure rather than requiring separate lateral space.

Inventive Principle:
Principle #5Merging (Combining)

2Area of stationary object

If the capacitor overlaps with the via, then the substrate size is reduced, but the dielectric layer deforms and breakdown voltage lowers

Engineering Contradiction:
Improvesubstrate sizeVSAvoidbreakdown voltage
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The invention introduces a pad as an intermediary structure between the capacitor and via. The pad fully covers the via and provides a stable platform for the capacitor, preventing direct contact between the capacitor electrodes and via metal. This intermediary layer isolates the capacitor dielectric from deformation caused by via formation processes, maintaining breakdown voltage while enabling compact overlapping layout.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the pad covers the via completely, then the electrical connectivity is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention segments the electrical connection structure into distinct functional layers: the via provides vertical connectivity through the substrate, the pad provides a covering platform that fully covers the via, and the capacitor provides capacitance function. This segmentation allows each component to be optimized independently while simplifying the overall manufacturing process through standardized formation steps.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10319634B2Semiconductor device having MIM capacitor
Publication Date: 2019.06.11 SUMITOMO ELECTRIC DEVICE INNOVATIONS
  • US10319634B2 patent drawing
  • US10319634B2 patent drawing
  • US10319634B2 patent drawing

AI summary

A semiconductor device that provides a pad electrically connected to the metal layer and a capacitor connected to the pad is disclosed. The semiconductor device provides an insulating film between the lower electrode of the capacitor and the pad. Because the insulating film protects and isolates the lower electrode from etching of the substrate via and deposition of the via metal, the lower electrode avoids voids or vacancies during formation of the via and the via metal.