MIM Capacitor Fabrication via Self-Aligned Etching
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Solution Overview
Problem
Conventional methods for fabricating MIM capacitors require additional masks for patterning, complicating the process and reducing economic benefits, while also limiting the ability to increase capacitance per unit area effectively.
Innovation Solution
A method involving sequential formation of conductive and dielectric layers with a mask layer and photoresist pattern, followed by selective etching to form electrodes, simplifies the fabrication process and enhances capacitance by eliminating the need for additional photoresist patterns and masks, using materials like silicon oxide or nitride for the mask layer and high dielectric constant materials for dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional methods are used to fabricate MIM capacitors with additional masks for patterning each electrode, then the capacitance per unit area can be increased, but the fabrication process becomes more complex and costly
Solution Approach 1:
The patent combines the patterning of multiple electrodes into a single photolithography step by forming all electrode patterns simultaneously using a unified photoresist layer and development process, eliminating the need for separate masks for each electrode while maintaining the multi-layer MIM capacitor structure
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional self-aligned patterning by forming side wall spacers and using vertical layer stacking, allowing multiple electrodes to be defined in different spatial dimensions without requiring additional lateral mask layers
2Manufacturing precision
If conventional methods with additional masks are used, then electrode patterning precision can be maintained, but fabrication time and cost increase
Solution Approach 1:
The patent performs preliminary formation of all electrode patterns and dielectric layers in a predetermined sequence before final patterning, allowing subsequent etching steps to proceed with high precision using a single mask layer while reducing the total number of fabrication cycles required
3Reliability
If monocrystalline or polycrystalline silicon is used for capacitor electrodes, then the electrode structure can be formed, but the resistance decreases and voltage stability deteriorates due to depletion region formation
Solution Approach 1:
The patent changes the material parameter of the electrode from monocrystalline or polycrystalline silicon to metal materials such as aluminum, copper, or tungsten, fundamentally altering the electrical properties to achieve low resistance and voltage-independent capacitance characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, decreases fabrication costs, and increases capacitance per unit area, improving RF properties and reducing signal loss in semiconductor devices.
Implementation Method 1
forming the second electrode by the sequentially patterning the mask layer, the conductive layer for the third electrode, the second dielectric layer, and the conductive layer using the photoresist pattern as an etching mask
Data Source
AI summary
Disclosed are methods of fabricating semiconductor devices. A method may include forming a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer. The method may also include forming a mask layer on the third conductive layer, forming a photoresist pattern on the mask layer, and forming at least one middle electrode by patterning the mask layer, the third conductive layer, the second dielectric layer, and the second conductive layer using the photoresist pattern as an etching mask. The method may also include forming a mask pattern by selectively etching a side wall of the patterned mask layer, removing the photoresist pattern, and forming an upper electrode by patterning the third conductive layer using the mask pattern as an etching mask.