MIM Capacitor Sidewall Protection for Clean Top Electrode Etching

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Solution Overview

Problem

The fabrication process of existing metal-insulator-metal (MIM) capacitors faces challenges in etching the top electrode, as a higher over-etching rate can damage the underlying TiN layer, while a lower over-etching rate results in TiN residues on the SiN film, compromising the integrity of the capacitor structure.

Innovation Solution

A novel MIM capacitor structure is designed with a first electrode layer comprising TiN and TaN layers, a silicon nitride dielectric layer, and a sidewall protection layer with TiON and aluminum oxide layers, along with a conformal dielectric cap layer, to protect the structure during etching and enhance fabrication precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a higher over-etching rate is used during top electrode etching, then etching speed is improved, but the underlying TiN layer is damaged

Engineering Contradiction:

Improveetching speedVSAvoidintegrity of underlying TiN layer

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A sidewall protection layer comprising TiON and aluminum oxide layers is deposited on the sidewalls of the second electrode layer. This intermediary protective structure allows the etching process to proceed at higher rates while preventing the etch plasma from directly damaging the underlying TiN layer, thus resolving the contradiction between etching speed and layer integrity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If a lower over-etching rate is used during top electrode etching, then the underlying TiN layer is protected, but TiN residues remain on the SiN film

Engineering Contradiction:

Improveintegrity of underlying TiN layerVSAvoidcleanliness of SiN film surface

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The sidewall protection layer serves as a controlled barrier that enables precise etching termination. By allowing higher etching rates with protection in place, the process achieves complete removal of the top electrode without leaving TiN residues on the SiN film, while still protecting the underlying TiN layer through the intermediary protective structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The etching process parameters are optimized to work in conjunction with the sidewall protection layer. The presence of the protection layer changes the effective etching parameters, allowing higher power and longer etching times without damaging the underlying layer, thereby achieving complete etching without residues.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If a sidewall protection layer is added to protect the TiN layer, then underlying layer integrity is improved, but device complexity increases

Engineering Contradiction:

Improveintegrity of underlying TiN layerVSAvoidnumber of layers in capacitor structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The sidewall protection layer is deposited in advance before the final etching step. This preliminary protective action ensures that when high-rate etching is performed, the underlying TiN layer is already protected, eliminating the need for complex in-situ protection mechanisms during etching.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The sidewall protection layer is implemented as a thin film structure that conformally coats the sidewalls of the electrode. This thin film approach provides effective protection without adding significant structural complexity or volume to the capacitor device.

Inventive Principle:

Principle #30Flexible shells and thin films

Data Source

PatentUS20260068195A1Metal-insulator-metal capacitor structure and fabrication method thereof

Publication Date: 2026.03.05 UNITED MICROELECTRONICS CORP

AI summary

A metal-insulator-metal (MIM) capacitor structure including a substrate; a first electrode layer disposed on the substrate; a first capacitor dielectric layer disposed on the first electrode layer; a second electrode layer disposed on the first capacitor dielectric layer; a sidewall protection layer disposed on a sidewall of the second electrode layer; and a dielectric cap layer conformally covering the first electrode layer, the sidewall protection layer, and the second electrode layer.