MIM Capacitor Structure With Self-Aligned Spacer for Footprint Matching

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Solution Overview

Problem

MIM capacitors in integrated chips face challenges in scaling their size without decreasing capacitance, leading to increased footprint and cost due to alignment tolerances between photomasks, causing the upper and lower electrodes to have significantly different footprints.

Innovation Solution

A method is developed to form MIM devices with upper and lower electrodes having similar footprints by using a self-aligned spacer to pattern the lower electrode layer, allowing for improved capacitance without increasing the overall footprint, achieved through a series of etching processes and spacer formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional photomask alignment methods are used to pattern MIM electrodes, then manufacturing process is simple, but the upper and lower electrodes have significantly different footprints leading to increased device footprint

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoiddevice footprint
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

A spacer structure is introduced as an intermediary element between the upper and lower electrode patterning processes. The spacer is formed on the upper electrode and serves as a self-aligned mask for patterning the lower electrode, ensuring precise footprint matching without requiring complex photomask alignment

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The spacer is formed in advance on the upper electrode before the lower electrode patterning step. This preliminary action establishes the exact footprint boundaries that the lower electrode must match, eliminating alignment tolerance issues that would otherwise require complex photomask procedures

Inventive Principle:
Principle #10Preliminary action

2Reliability

If electrode footprint is increased to maintain capacitance during scaling, then capacitance is preserved, but device footprint increases leading to higher cost

Engineering Contradiction:
ImprovecapacitanceVSAvoiddevice footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The spacer structure serves itself as a patterning mask for the lower electrode, automatically ensuring that the lower electrode footprint matches the upper electrode footprint. This self-aligned approach eliminates the need for separate alignment procedures and ensures precise footprint matching while maintaining capacitance

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If photomask alignment tolerance is relaxed for simpler manufacturing, then manufacturing precision decreases, but electrode footprint mismatch increases causing potential electrical shorting

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidelectrical isolation
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The spacer acts as an intermediary that physically defines the boundary between the upper and lower electrodes. By using the spacer as a self-aligned mask, the lower electrode is precisely patterned to match the upper electrode footprint, preventing any overlap that could cause electrical shorting while maintaining simple manufacturing

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12154939B2High capacitance MIM device with self aligned spacer
Publication Date: 2024.11.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12154939B2 patent drawing
  • US12154939B2 patent drawing
  • US12154939B2 patent drawing

AI summary

The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.