MIM Capacitor Spacer Patterning for Matched Electrode Footprints

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Solution Overview

Problem

MIM capacitors in integrated chips face challenges in scaling their size without decreasing capacitance, leading to increased footprint and cost due to alignment tolerances between photomasks, causing the upper and lower electrodes to have significantly different footprints.

Innovation Solution

A method is introduced to form MIM devices with upper and lower electrodes having similar footprints by using a self-aligned spacer to pattern the lower electrode layer, allowing for improved capacitance without increasing the overall footprint, achieved through a series of etching processes and spacer formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional photomask alignment methods are used to pattern upper and lower electrodes, then manufacturing process is simple, but alignment tolerances cause significantly different footprints between upper and lower electrodes, decreasing capacitance

Engineering Contradiction:

Improveelectrode footprint alignmentVSAvoidpatterning process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

A spacer layer is introduced as an intermediary element between the upper electrode and lower electrode patterning processes. The spacer is formed conformally on the upper electrode and then used as a mask to define the lower electrode footprint, ensuring precise alignment without requiring high-precision photomask alignment. This intermediary structure resolves the contradiction by decoupling the alignment precision requirement from the photomask process.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The upper electrode is patterned first, and then the spacer is formed conformally on it before the lower electrode is patterned. This preliminary formation of the upper electrode and spacer structure provides a pre-defined alignment reference for the lower electrode, eliminating the need for complex photomask alignment and ensuring matching footprints that maximize capacitance.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If electrode footprint area is increased to maintain capacitance during scaling, then capacitance is maintained, but overall device footprint increases, increasing chip area and cost

Engineering Contradiction:

Improvecapacitance performanceVSAvoiddevice footprint

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent creates a symmetric footprint relationship between upper and lower electrodes through the spacer-based patterning method, where both electrodes have substantially equal footprints. This asymmetric approach to achieving symmetry (using a spacer intermediary rather than direct photomask alignment) allows for optimized capacitance density without increasing overall device footprint, resolving the contradiction between maintaining capacitance and minimizing area.

Inventive Principle:

Principle #4Asymmetry

3Ease of manufacture

If etching processes are used to pattern electrodes, then manufacturing is feasible, but conductive byproducts may cause electrical shorting between upper and lower electrodes

Engineering Contradiction:

Improveelectrode patterning feasibilityVSAvoidconductive byproduct shorting

Core Design Contradiction:

Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The spacer structure is used to extract and isolate the harmful conductive byproducts from the electrode interface. During the lower electrode etching process, byproducts are deposited on the spacer rather than directly on the upper electrode, preventing shorting. The spacer acts as a protective barrier that extracts the harmful effect from the critical electrode region.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The spacer serves as a protective intermediary layer between the etching process and the upper electrode. It absorbs and contains the conductive byproducts generated during lower electrode patterning, preventing them from causing electrical shorting between electrodes while allowing the etching process to proceed effectively.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11769791B2High capacitance MIM device with self aligned spacer

Publication Date: 2023.09.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.