MIM Capacitor Trench Layout for Higher Capacitance Density
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Solution Overview
Problem
Existing capacitive elements in integrated circuits face limitations in maximizing surface capacity due to restricted etching depths and costs associated with deep trench etching tools, which restrict the increase of capacitive value per surface unit.
Innovation Solution
Incorporating metal-insulator-metal (MIM) capacitive structures within the pre-metal dielectric region of integrated circuits, utilizing a conductive layer of polycrystalline silicon with a metal silicide diffusion barrier, and forming trenches to increase the interface area between metal layers, while also creating a metal-oxide-semiconductor (MOS) capacitive structure without occupying additional substrate space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If trenches are etched deeper to increase surface capacity, then capacitive value per surface unit increases, but etching time increases proportionally and tool integration cost increases
Solution Approach 1:
The patent transitions from increasing trench depth (vertical dimension) to utilizing the lateral dimension by forming MIM capacitive structures within the pre-metal dielectric region. This allows capacitive elements to be integrated in the horizontal plane without requiring deeper trenches, thereby avoiding increased etching time while maintaining or improving capacitive value per surface unit.
Solution Approach 2:
The pre-metal dielectric region, traditionally serving only as an insulating layer, is repurposed to host MIM capacitive structures. This multi-functional use of the same region allows capacitive elements to be formed without additional processing steps for deep trench etching, reducing both time and cost while increasing capacitive value.
2Quantity of substance
If trenches are etched deeper to increase surface capacity, then capacitive value per surface unit increases, but integration cost of deep trench etching tools increases
Solution Approach 1:
The patent shifts from vertical expansion (deeper trenches) to lateral utilization by integrating MIM capacitive structures in the pre-metal dielectric region. This approach uses existing fabrication capabilities without requiring expensive deep trench etching tools, thereby reducing integration cost while maintaining capacitive value.
Solution Approach 2:
The patent uses standard MIM capacitor fabrication processes that are already established in the industry, copying proven manufacturing techniques rather than developing new deep trench etching methods. This leverages existing tooling and process knowledge, avoiding the need for costly new equipment integration.
3Area of stationary object
If MIM capacitive structures are integrated in the pre-metal dielectric region, then additional capacitive interface is obtained without additional substrate space, but spatial constraints from other elements increase
Solution Approach 1:
The patent applies local quality by selectively forming MIM capacitive structures in specific areas of the pre-metal dielectric region where spatial constraints are more tolerable. This allows optimization of capacitive density in regions with sufficient headroom while maintaining other circuit elements in regions with tighter constraints, balancing spatial stress across the substrate.
4Area of moving object
If trenches are etched to form MIM capacitive structures, then interface area between metal layers increases, but etching process complexity increases
Solution Approach 1:
The patent uses the pre-metal dielectric region etching process to serve dual purposes: creating access holes for metal contacts and forming trenches for MIM capacitive structures. This multi-functional use of the same etching step increases interface area without adding separate etching processes, thereby avoiding increased process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances capacitive value by maximizing the interface area between conductive layers, allowing for increased capacitive performance without additional substrate space and integrating with existing production lines, thereby reducing costs and spatial constraints.
Implementation Method 1
the first metal layer comprises a diffusion barrier layer in chemical bond with the thin layer of metal silicide
Data Source
AI summary
An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.