MIM Capacitor Via Structure for Simpler BEOL Integration
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Solution Overview
Problem
The existing integrated circuit (IC) back end-of-line (BEOL) fabrication processes face challenges in efficiently integrating metal-insulator-metal (MIM) capacitors into the metallization structure, which increases process costs and cycle time, and requires additional steps that complicate the integration with other components like contact pads and vias.
Innovation Solution
The integration of MIM capacitor fabrication into the fabrication of big vias and other vias connecting with the top metal layer, where both the bottom and top capacitor metals comprise the same via material as the electrical vias, allowing the MIM capacitor to be considered as a via with an insulator layer dividing it into two terminals, thereby simplifying the fabrication process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MIM capacitor fabrication is integrated into existing BEOL processes, then process costs and cycle time are reduced, but the integration complexity with contact pads and vias increases
Solution Approach 1:
The patent merges MIM capacitor fabrication with via fabrication by using the same via material for both bottom and top capacitor metals, and treating the capacitor as a via with an insulator layer dividing it into two terminals. This consolidation eliminates separate fabrication steps for capacitors, directly reducing cycle time and process costs while the standardized via-based approach actually simplifies integration complexity
Solution Approach 2:
The via material serves multiple functions: it forms both the electrical vias connecting metal layers and the bottom and top capacitor metals of the MIM capacitor. This multi-functionality reduces the number of material depositions and process steps required, improving productivity without adding integration complexity
2Ease of manufacture
If MIM capacitor fabrication is integrated into existing BEOL processes, then process costs are reduced, but additional steps are required that complicate integration with other components
Solution Approach 1:
The fabrication process merges capacitor creation with via creation by depositing via material that forms both electrical vias and capacitor electrodes simultaneously. The insulator layer is deposited as part of the standard via formation sequence, dividing the via into two terminals that function as capacitor plates. This merging eliminates dedicated capacitor fabrication steps, reducing both costs and process complexity
Solution Approach 2:
The via fabrication process itself serves to create the MIM capacitor structure. By treating the capacitor as a specialized via with an insulator layer, the existing via formation steps automatically create the capacitor electrodes and connections, eliminating the need for separate capacitor-specific fabrication steps and reducing overall process complexity
Data Source
AI summary
A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.