Mini-LED Display Panel Single-Layer Wiring to Prevent Short Circuits
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Solution Overview
Problem
In current mini-LED display technologies, the disposition of metal wirings in multiple layers leads to a high propensity for short circuits, resulting in increased costs and performance issues.
Innovation Solution
The display panel design includes a power line, grounding signal wiring, driving chips, and light-emitting lamp groups, where all these components are disposed in the same layer, with partition channel wirings connecting the light-emitting lamp groups to the driving chips, thereby preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If metal wirings are disposed in multiple layers, then wiring functionality is improved, but short circuit risk increases
Solution Approach 1:
The patent transitions from multi-layer wiring arrangement to single-layer wiring arrangement, changing the dimensional organization of conductors. All metal wirings (power line, grounding signal wiring, partition channel wirings) are disposed in the same layer, eliminating vertical stacking and thereby eliminating short circuit risks between layers while maintaining wiring functionality through careful lateral spacing and arrangement.
2Device complexity
If grounding wiring, partition channel wirings, and power wiring are disposed in different layers, then wiring organization is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple wiring types (power line, grounding signal wiring, partition channel wirings) into a single layer, consolidating what would traditionally require multiple layers. This merging simplifies the manufacturing process by reducing the number of layer deposition and alignment steps, thereby lowering manufacturing costs while maintaining functional organization through lateral spacing and designated regions within the single layer.
Data Source
AI summary
A display panel is provided, including a power line, light-emitting lamp groups, partition channel wirings, driving chips, and a grounding signal wiring. The driving chips, the light-emitting lamp groups, and the partition channel wirings are disposed between the power line and the grouping signal wiring spaced apart. The driving chips are connected to the grounding signal wiring. The light-emitting lamp groups are connected to the power line. The partition channel wirings are connected to the light-emitting lamp groups. The power line, the grounding signal wiring, and the partition channel wirings are disposed in a same layer.


