Minimum Track Standard Cell Circuits Using High Aspect Ratio Voltage Rails
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Solution Overview
Problem
Conventional standard cell circuits face limitations in achieving area reduction as technology node size scales down to 10 nm or less due to constraints in metal line scaling, leading to increased resistance and voltage drop, which prevents further area minimization.
Innovation Solution
The implementation of minimum track standard cell circuits using high aspect ratio voltage rails with a height-to-width ratio greater than one, allowing for reduced width consumption while maintaining similar resistance, and employing fewer tracks for metal line routing, resulting in a five-track configuration compared to the conventional six-track design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If metal lines are scaled down to reduce area, then area is reduced, but resistance increases and voltage drop increases
Solution Approach 1:
The patent transitions from two-dimensional metal line routing to three-dimensional vertical voltage rails. By extending voltage rails vertically through multiple metal layers (achieving height-to-width ratios greater than one), the design compensates for the resistance increases caused by horizontal scaling, maintaining voltage stability while enabling continued area reduction.
Solution Approach 2:
The patent changes the geometric parameters of voltage distribution structures by creating high aspect ratio vertical rails rather than horizontal lines. This parameter change from width-dominated to height-dominated structures allows the circuit to maintain acceptable resistance characteristics even as overall dimensions are scaled down.
2Area of stationary object
If technology node size is scaled down, then area is reduced, but metal line scaling is limited by gate pitch and metal pitch constraints
Solution Approach 1:
The patent resolves manufacturing constraints by moving the scaling solution into the vertical dimension. Instead of attempting to scale horizontal metal line dimensions below fabrication limits, the design uses vertical extension through stacked metal layers, which can be manufactured using standard multi-layer CMOS processes without violating pitch constraints.
Solution Approach 2:
The patent nests voltage rails across multiple metal layers, with each layer contributing to the vertical structure. This nested arrangement through the metal stack allows the voltage distribution network to achieve the required electrical performance while conforming to the minimum feature size constraints of the fabrication process.
Data Source
AI summary
Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.