Minimum-Width Resistor Doping for Cross-Wafer Resistance Uniformity

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Solution Overview

Problem

CMOS resistor fabrication processes, particularly polysilicon deposition and patterning, result in significant resistance variations across the wafer, leading to increased variability and testing costs due to small linewidth changes having a larger effect on resistance.

Innovation Solution

A method combining dilution doping with an exposure map that defines variable photoresist exposure doses and times across target regions on the wafer to compensate for process variations, using a reticle with multiple openings and dopant blocking regions to control the size of openings and dopant distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If minimum width resistors are used to reduce device area, then area is reduced, but resistance variability increases significantly

Engineering Contradiction:
Improveresistor areaVSAvoidresistance variability
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by varying the dopant concentration across different regions of the wafer. The exposure map divides the wafer into multiple regions, each with customized exposure doses and dopant concentrations tailored to local process variations, thereby maintaining consistent resistance values across the entire wafer even with minimum width dimensions

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes multiple parameters simultaneously: exposure dose, exposure time, and dopant concentration are all varied across different wafer regions according to the exposure map. This multi-parameter adjustment compensates for process variations and enables minimum width resistors to achieve target resistance values with reduced variability

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If uniform exposure dose is used across the wafer, then process simplicity is maintained, but resistance variability across wafer increases

Engineering Contradiction:
Improveprocess simplicityVSAvoidresistance uniformity across wafer
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the wafer into multiple target regions or shots, each with its own exposure parameters defined in an exposure map. This segmentation allows customization of exposure doses and dopant concentrations for each region, compensating for local process variations while maintaining a systematic approach that integrates into existing fabrication workflows

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic adjustment of exposure parameters across the wafer. Rather than a static uniform dose, the exposure map provides dynamic, location-specific exposure doses and times, allowing the process to adapt to spatial variations in polysilicon deposition and other manufacturing parameters

Inventive Principle:
Principle #15Dynamics

3Reliability

If small variations in polysilicon linewidth occur, then deposition process tolerance is maintained, but resistance variability increases for minimum width resistors

Engineering Contradiction:
Improvedeposition process stabilityVSAvoidresistance control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent compensates for linewidth variations by changing dopant concentration parameters. The exposure map calculates required dopant concentrations based on local linewidth measurements and process variations, then applies customized exposure doses to achieve target resistance values despite variations in polysilicon geometry

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces resistance variability across the wafer, allowing for more consistent resistor properties and lower testing costs by customizing dopant exposure for each region, thereby enhancing the fabrication of integrated circuits.

Implementation Method 1

exposing a respective target region using a reticle that defines a first exposure window

Methodology Applied
Scientific EffectPhotoabsorption: Absorption (EM radiation)

Implementation Method 2

implanting a dopant into the substrate through the first plurality of openings

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS11764111B2Reducing cross-wafer variability for minimum width resistors
Publication Date: 2023.09.19 TEXAS INSTRUMENTS INC
  • US11764111B2 patent drawing
  • US11764111B2 patent drawing
  • US11764111B2 patent drawing

AI summary

Fabrication of an integrated circuit includes forming a photoresist layer over a substrate. Target regions defined on the substrate are exposed using a reticle that defines a first exposure window for a first doped structure of a first type; the first exposure window has a first plurality of openings and a first plurality of dopant blocking regions. A respective exposure dose for each of the target regions is determined by an exposure map and provides controlled variations in the size of the first plurality of openings across the plurality of target regions. Subsequent to the exposure and to developing the photoresist, a dopant is implanted into the substrate through the first plurality of openings.