Mirrored DDR5 Memory Module Layout for Address Signal Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory modules face challenges in efficiently transmitting address signals due to limitations in reducing cell size and capacity, particularly in dynamic random access memory (DRAM) devices, which hinder high-capacity implementations within a limited area.
Innovation Solution
A memory module design with a control device that symmetrically transmits address signals to groups of semiconductor memory devices through physically symmetric transmission lines, utilizing a selective address mirroring circuit that swaps certain bits of the address signal based on the voltage level of a mirror pin, enabling mirrored or standard modes of operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple DRAMs are provided in a memory module to achieve high capacity, then storage capacity is improved, but address signal transmission efficiency deteriorates
Solution Approach 1:
The memory module is divided into multiple groups of semiconductor memory devices, with each group receiving address signals through dedicated transmission lines. This segmentation allows independent signal routing to different memory regions, improving transmission efficiency while maintaining high capacity through multi-group configuration
Solution Approach 2:
The patent introduces physically symmetric transmission lines with respect to an axis intersecting the control device, creating mirrored address signal paths. This symmetric design optimizes signal transmission by balancing the routing paths to different memory groups, reducing signal skew and improving overall transmission efficiency
2Area of moving object
If DRAM cell size is reduced to increase capacity within limited area, then area density is improved, but cell structure complexity increases
Solution Approach 1:
The patent addresses the area constraint by transitioning from a single-plane layout to a three-dimensional configuration, stacking multiple groups of semiconductor memory devices vertically. This dimensional change allows high capacity within limited area without increasing planar cell complexity, as the additional capacity is achieved through vertical integration rather than expanding lateral footprint
Data Source
AI summary
A memory module includes semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group and the second group through a first transmission line and a second transmission line, respectively. The first transmission line and the second transmission line are physically symmetric with respect to an axis intersecting the control device.