Semiconductor MISR Clock Change-Over Unit for Low-Speed Testing
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Solution Overview
Problem
The high cost of manufacturing semiconductor integrated circuits is attributed to the need for high-speed LSI testers capable of handling the high-frequency clock signals required for testing, which are expensive and complex due to the necessity of precise analysis.
Innovation Solution
A semiconductor integrated circuit with a clock signal change-over unit that operates using a first high-speed clock signal for data storage and a second lower-frequency clock signal for data read-out and output, allowing for data compression and testing with a low-speed LSI tester.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed LSI tester is used to test data output at high frequency, then test speed and data output speed are improved, but manufacturing cost increases due to the high cost of high-speed testers
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable and changeable based on operational mode. The clock signal changes from a first frequency during data storage to a second frequency during data readout, allowing the system to adapt its speed characteristics to different operational requirements rather than operating at a fixed high speed throughout
Solution Approach 2:
The patent changes the frequency parameter of the clock signal based on the operational phase. During data storage, a first clock frequency is used, and during data readout, a second clock frequency is used. This parameter change allows the system to optimize performance for each phase while reducing the overall speed requirements for testing
2Speed
If a high-frequency clock signal is used for data storage and output, then data processing speed is improved, but device complexity increases due to the need for high-speed input/output buffers
Solution Approach 1:
The clock signal frequency is dynamically adjusted based on the operational mode. The system uses a first frequency during data storage operations and switches to a second frequency during data readout operations, allowing the input/output buffers to operate at lower speeds during readout phases and reducing their complexity requirements
Solution Approach 2:
The frequency parameter of the clock signal is changed based on operational phase. By using different frequencies for different operations, the system reduces the maximum speed requirement for the input/output buffers, thereby reducing their complexity while maintaining data processing performance
3Reliability
If a high-speed LSI tester is used for testing, then test reliability is maintained, but current consumption increases
Solution Approach 1:
The clock signal frequency is dynamically changed based on the operational mode. During data storage, a first frequency is used, and during data readout, a second frequency is used. This dynamic frequency adjustment allows the system to maintain test reliability during critical operations while reducing current consumption during data readout operations
Solution Approach 2:
The frequency parameter of the clock signal is changed based on operational requirements. By using lower frequencies during data readout phases, the system reduces current consumption while maintaining test reliability during data storage and processing phases where high frequency is critical
Data Source
AI summary
A semiconductor integrated circuit includes an MISR (Multiple-Input Signature Register) for generating and storing compressed code based upon code from a ROM, and for reading out and outputting the compressed data that has been stored. The MISR has a clock change-over unit for changing over a clock in such a manner that the MISR is caused to operate at a high-speed clock when the compressed data is generated and stored, and at a low-speed clock when the stored compressed data is read out and output.