Thin-Film Transistor Layout With Mixed Channel Angles for Display Integration
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Solution Overview
Problem
Existing display apparatuses face challenges in achieving high integration and reliability while maintaining high-quality image display.
Innovation Solution
The display apparatus incorporates a substrate with a first thin-film transistor having a semiconductor layer with a channel region angle of 0° to 5° relative to the substrate, and a second thin-film transistor with a semiconductor layer having a channel region angle of 20° to 90°, both sharing the same gate electrode layer. This configuration includes a lower conductive layer, insulating layers, and a storage capacitor to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single gate electrode layer is used for both horizontal and vertical channel transistors, then manufacturing complexity is reduced and integration is improved, but the geometric configuration becomes more complex to accommodate different channel angles
Solution Approach 1:
The patent applies local quality by configuring the first semiconductor layer with a channel region angle of 0° to 5° (horizontal channel) while the second semiconductor layer has a channel region angle of 20° to 90° (vertical channel). This allows each transistor to have optimized local geometric properties suitable for its function while sharing the same gate electrode layer, resolving the contradiction between device complexity and ease of manufacture.
2Productivity
If horizontal and vertical channel transistors are integrated in the same layer, then integration density is improved, but the geometric configuration complexity increases
Solution Approach 1:
The patent resolves the geometric configuration complexity by transitioning from a two-dimensional planar view to a three-dimensional stacked view. The first and second semiconductor layers are positioned at different heights above the substrate, with the first insulating layer separating them vertically. This dimensional transition allows high integration density while managing geometric complexity through vertical stacking rather than planar arrangement.
3Reliability
If different channel region angles are used for different transistors, then transistor performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by defining specific angle ranges for the channel regions: 0° to 5° for the first semiconductor layer and 20° to 90° for the second semiconductor layer. These parameter specifications optimize transistor performance for different operational requirements while providing clear manufacturing targets that balance performance improvement with achievable manufacturing precision.
Data Source
AI summary
A display apparatus is disclosed that includes a substrate, a first thin-film transistor, a second thin-film transistor, and a lower conductive layer. The first thin-film transistor is located on the substrate and includes a first semiconductor layer and a first gate electrode. The second thin-film transistor is located on the substrate and includes a second semiconductor layer, a second gate electrode, a lower electrode, and an upper electrode. The lower conductive layer is located between the substrate and the first semiconductor layer. A first angle between a channel region of the first semiconductor layer and the substrate is different from a second angle between a channel region of the second semiconductor layer and the substrate. The first gate electrode and the second gate electrode are located on a same layer.