Unified Scan Clock Generation for Mixed Flip-Flop Types
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit devices typically employ either MuxD or LSSD flip-flops for scan testing, limiting their ability to integrate both types into a common scan chain due to different clocking schemes, which affects shift speed and timing alignment.
Innovation Solution
The solution involves generating aligned scan clock signals for both MuxD and LSSD flip-flops, allowing them to be integrated into a common scan chain, with external or internal scan clock modes, and using a shared clock distribution network to simplify wire routing and ensure timing alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LSSD flip-flops are used for scan testing, then setup timing requirements are met and hold timing violations are resistant, but device complexity increases due to dedicated non-overlapping clock signals
Solution Approach 1:
The patent implements a universal clock distribution network that serves dual purposes: providing functional clock signals for normal operation and generating scan clock signals for testing. The same clock tree infrastructure is used for both LSSD and MuxD flip-flops, eliminating the need for separate dedicated scan clock distribution networks. This multi-functional approach reduces device complexity while maintaining timing reliability.
Solution Approach 2:
The patent dynamically changes the clock signal parameters (phase, frequency, overlap) based on the operational mode. During normal operation, the clock distribution network provides standard functional clocks. During scan testing, the same network generates aligned scan clock signals with adjusted parameters to accommodate both LSSD and MuxD flip-flop timing requirements, thereby reducing structural complexity.
2Device complexity
If MuxD flip-flops are used for scan testing, then device complexity is reduced with single clock port, but shift speed is impacted due to conservative buffering of scan paths
Solution Approach 1:
The patent applies different clocking strategies to different flip-flop types within the same scan chain. LSSD flip-flops receive aligned non-overlapping scan clock signals that enable faster shifting, while MuxD flip-flops receive coordinated clock signals that maintain compatibility. This localized optimization allows high-speed scanning in LSSD regions without compromising the overall simplicity of the clocking architecture.
Solution Approach 2:
The clock distribution network dynamically adjusts clock signal characteristics based on the scan chain segment being tested. When scanning through LSSD flip-flops, the system enables higher shift speeds with properly aligned non-overlapping clocks. When encountering MuxD flip-flops, the system coordinates clock signals to maintain proper multiplexing operation. This dynamic adaptation allows the system to achieve high speeds where possible while maintaining architectural simplicity.
3Reliability
If separate clock distribution networks are used for MuxD and LSSD flip-flops, then timing alignment is ensured, but wire routing complexity increases
Solution Approach 1:
The patent merges the functional clock distribution network and scan clock distribution network into a single unified clock tree structure. The same physical clock distribution infrastructure is used to provide both functional clocks for normal operation and scan clocks for testing. Time alignment is achieved through coordinated control logic that generates properly phased scan clock signals from the existing clock tree, eliminating the need for separate dedicated scan clock routing.
Solution Approach 2:
The unified clock distribution network is designed to be universal, serving dual functions: providing functional clocks during normal operation and generating scan clocks during testing. This multi-functional design eliminates redundant wiring and reduces the overall clock distribution structure complexity while maintaining precise timing alignment through coordinated signal generation.
4Device complexity
If a single type of flip-flop is used for an entire clock domain, then device complexity is minimized, but adaptability to different testing requirements is reduced
Solution Approach 1:
The patent segments the scan chain into different regions containing LSSD and MuxD flip-flops, allowing each segment to be optimized for its specific requirements. The clock distribution network is coordinated to provide appropriately timed signals for each segment type. This segmentation enables the system to maintain testing flexibility and adaptability while keeping the overall device complexity manageable through modular design.
Solution Approach 2:
The system dynamically adapts the clock signals based on the flip-flop type being scanned. The clock distribution network incorporates control logic that adjusts clock phase, frequency, and overlap parameters in real-time depending on whether LSSD or MuxD flip-flops are being scanned. This dynamic adaptation enables a single unified clock domain to support multiple flip-flop types and testing requirements without requiring separate clock domains.
Data Source
AI summary
An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. A method includes generating a first scan clock signal for loading scan data into at least one flip flop of a first type, generating a second scan clock signal and a third scan clock signal for loading the scan data into at least one flip flop of a second type, and loading a test pattern into a scan chain defined by the at least flip flop of the first type and the at least one flip flop of the second type responsive to the first, second, and third scan clock signals.