Mixed Static-Dynamic Logic Circuit With Phase-Adjusted Clocking
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Solution Overview
Problem
Integrated circuits with both static and dynamic combinational circuits face operational issues due to asynchronous clock signals, leading to incorrect data processing and failure in normal operation after clock tree balancing.
Innovation Solution
Incorporating a multi-phase generator to dynamically adjust the clock signal delay, ensuring the dynamic combinational circuit receives intermediate data from the static combinational circuit correctly, thereby enabling normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a mixed circuitry structure of static combinational circuit and dynamic combinational circuit is used, then the circuit functionality and processing capability are improved, but the clock signal synchronization becomes problematic leading to operational failure
Solution Approach 1:
The patent segments the clock signal distribution into two independent paths: one path delivers the clock signal to the static combinational circuit, while another path delivers a phase-adjusted clock signal to the dynamic combinational circuit. This segmentation allows each circuit type to receive appropriately timed clock signals, resolving the synchronization conflict between static and dynamic circuit operations
Solution Approach 2:
The patent introduces a delay element as an intermediary component in the clock signal path to the dynamic combinational circuit. This delay element acts as a mediator that adjusts the timing of the clock signal, ensuring that the dynamic combinational circuit receives the clock signal at the correct phase relative to the static combinational circuit, thereby enabling proper synchronization without direct coupling between the circuits
2Stability of the object's composition
If clock tree balancing is performed to synchronize clock signals, then the clock distribution is optimized, but the dynamic combinational circuit fails to receive correctly timed signals
Solution Approach 1:
The patent applies different clock signal characteristics to different parts of the circuit: the static combinational circuit receives a standard clock signal, while the dynamic combinational circuit receives a clock signal with adjusted phase timing. This local differentiation allows each circuit component to operate with the specific clock timing it requires, resolving the conflict between overall synchronization and local operational correctness
Data Source
AI summary
An integrated circuit includes a first stage and a second stage. The first stage receives a previous stage output data and a clock signal and generates a first output data. The second stage receives the first output data and the clock signal. The first stage includes a first flip-flop circuit, a first static combinational circuit, a dynamic combinational circuit and a multi-phase generator. The first flip-flop circuit receives the previous output data and the clock signal and generates an input data. The first static combinational circuit receives the input data and generates an intermediate data. The multi-phase generator receives the clock signal and generates a delayed clock signal. The dynamic combinational circuit receives the intermediate data and the delayed clock signal and generates the first output data.