Adaptive Mixed-Mode DLL Locking for Jitter-Tolerant Phase Detection
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Solution Overview
Problem
Existing Delay-Locked Loop (DLL) circuits in high-speed digital systems face challenges in maintaining a locked state due to jitter and noise, leading to poor jitter performance and frequent re-locking processes that worsen output clock jitter.
Innovation Solution
The implementation of a mixed-mode DLL circuit with adaptive digital and analog delay loop functions, including a digital phase detector and an analog phase detector, which initially achieves phase-locking and then adjusts the phase detection window and frequency to maintain lock in noisy environments, preventing transition back to the unlocked state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DLL circuit uses a fixed phase detection window and frequency, then the circuit structure is simple, but the circuit cannot maintain locked state in noisy environments leading to poor jitter performance
Solution Approach 1:
The patent implements adaptive phase detection by dynamically adjusting the phase detection window width and sampling frequency based on lock status. When unlocked, a narrow window and high frequency enable fast acquisition. When locked, a wide window and lower frequency maintain stability against jitter and noise, preventing false unlock conditions.
Solution Approach 2:
The system changes operational parameters (phase detection window width and sampling frequency) based on the lock status of the DLL circuit. This allows the circuit to optimize its performance for different states: fast locking when unlocked, and robust jitter rejection when locked, thereby improving overall reliability without requiring a completely complex circuit architecture.
2Speed
If the phase detection window is narrow for fast locking, then locking speed is improved, but the circuit becomes sensitive to jitter and noise causing frequent re-locking
Solution Approach 1:
The phase detection window width is dynamically adjusted based on lock status. During initial locking, a narrow window provides fast response. Once locked, the window automatically widens to accommodate jitter and noise, preventing false unlock detections and re-locking events, thus improving jitter performance while maintaining fast initial acquisition.
Solution Approach 2:
The system employs periodic phase detection at adaptively adjusted frequencies. When unlocked, high-frequency detection enables rapid lock acquisition. When locked, the detection frequency is reduced while maintaining a wider window, which filters out high-frequency jitter and noise, thereby improving overall jitter performance without sacrificing initial locking speed.
3Loss of time
If the phase detection frequency is high for fast acquisition, then locking time is reduced, but timing margins deteriorate in noisy environments
Solution Approach 1:
The phase detection sampling frequency is dynamically adjusted based on lock status. High frequency sampling is used during initial acquisition to minimize locking time. Once locked, the frequency is reduced while the phase detection window is widened, which improves timing margins by filtering out high-frequency noise and jitter, thereby maintaining reliability in noisy environments.
4Reliability
If the phase detection window is wide to tolerate jitter, then jitter resistance is improved, but locking speed decreases
Solution Approach 1:
The phase detection window width is dynamically controlled based on whether the DLL is locked or unlocked. When unlocked, the window is narrow to provide fast detection and reduce locking time. When locked, the window automatically widens to tolerate jitter and noise, improving jitter resistance. This dynamic adjustment resolves the contradiction between fast locking and jitter tolerance.
Data Source
AI summary
Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.