33% Duty-Cycle Mixer Clocking for Third-Harmonic Suppression
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Solution Overview
Problem
Mixer circuits in integrated circuits face issues with undesired spurs or signals, particularly third-order harmonics, which affect performance, especially in frequency bands like LTE band 13, and existing solutions either increase complexity, cost, or power consumption.
Innovation Solution
A mixer circuit utilizing non-overlapping clock signals with a 33⅓ percent duty cycle and I-Q quadrature baseband inputs, combined with voltage sampling and three-phase clock signals, effectively suppresses third-order harmonics and I-Q quadrature image signals, achieving high linearity without the need for additional filters or power amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a band pass filter is coupled between the mixer and PA driver to remove IM3 signal, then the undesired spur is reduced, but the circuit complexity and chip area increase
Solution Approach 1:
The patent extracts and eliminates the third-order harmonic component at its source within the mixer circuit by using a three-phase clock signal arrangement. Instead of adding external filtering components, the design removes the harmful IM3 signal through careful phase management of the clock signals driving the mixer elements, thereby avoiding increased circuit complexity while achieving spur reduction
Solution Approach 2:
The patent introduces three-phase clock signals as an intermediary mechanism to suppress unwanted harmonics. These clock signals with specific phase relationships (0°, 120°, 240°) act as mediators that cancel out the third-order harmonic components through destructive interference, eliminating the need for additional filtering hardware
2Object-generated harmful factors
If a saw filter is coupled between the PA driver and PA to remove undesired spur, then the spur is reduced, but the packaging area and cost increase
Solution Approach 1:
The patent extracts the harmonic suppression function from external filtering components and implements it directly within the mixer circuit through three-phase clock signaling. This eliminates the need for separate SAW filters or other external filtering components that would increase packaging area and device cost
Solution Approach 2:
The patent merges the harmonic suppression function with the existing mixer circuit operation by using three-phase clock signals. Instead of adding separate filtering stages that would increase packaging area, the suppression mechanism is combined with the signal mixing operation itself, achieving dual functionality without additional space
3Object-generated harmful factors
If an active harmonic rejection mixer is used to suppress harmonics, then the spur reduction is achieved, but the power consumption and area increase
Solution Approach 1:
The patent employs periodic three-phase clock signals with specific duty cycles and phase relationships to suppress harmonics. By using non-overlapping periodic clock phases (0°, 120°, 240°), the circuit achieves harmonic rejection through time-division multiplexing of the mixing operation, avoiding the need for continuous active suppression that would increase power consumption
Solution Approach 2:
The patent changes the clock signal parameters (phase relationships and duty cycles) to achieve harmonic suppression. By carefully selecting the clock phase offsets (120° apart) and duty cycles, the system suppresses unwanted harmonics through parameter optimization rather than requiring additional active suppression circuits that would increase power consumption
4Device complexity
If conventional mixers are used, then the circuit is simple, but undesired spurs and third-order harmonics are produced
Solution Approach 1:
The patent introduces asymmetry in the clock signal phases (three distinct phases at 0°, 120°, and 240°) to suppress harmonics while maintaining circuit simplicity. This asymmetric phase arrangement creates destructive interference for third-order harmonics without requiring complex additional circuitry, achieving harmonic suppression with minimal added complexity
Data Source
AI summary
A mixer circuit is disclosed. The mixer circuit comprises a plurality of mixer elements, wherein there are non-overlapping clock signals provided to the plurality of mixer elements which have a duty cycle of 33⅓ percent. Outputs signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. The third-order harmonic of the mixer is eliminated by using mixer which uses voltage sampling on non-overlapping clocks and thereby achieves high linearity. The mixer circuit is further expanded to remove the I-Q image and even order harmonics.