Unified ML Verification Infrastructure for DUT Validation Reuse
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Solution Overview
Problem
Current testing methods for electronic devices under testing (DUT) lack reusability across different platforms, leading to redundancy and inefficiency as different teams reinvent stimulus and validation approaches for hardware simulation, emulation, and post-silicon validation.
Innovation Solution
A unified software/compiler-independent end-to-end machine learning (ML) verification infrastructure is proposed, utilizing an inference profile, static and dynamic verification of math functions, and an inference database to generate reusable validation models across multiple platforms, enabling efficient stimulus, DUT configuration, and output prediction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different teams generate their own stimulus across various platforms (software simulation, hardware emulation, post-silicon validation), then each team can customize validation for their specific platform, but this leads to redundancy and lack of reusability of validation approaches
Solution Approach 1:
The patent creates a universal stimulus generation system that can operate across multiple platforms (software simulation, hardware emulation, post-silicon validation) through a common architecture. The stimulus generator uses platform-agnostic DUT specifications and instruction sets to produce validation stimuli that are reusable across all platforms, eliminating the need for each team to build custom validation infrastructure while maintaining platform-specific adaptability through configurable platform interfaces
2Ease of operation
If teams reinvent the wheel by building their own validation platforms, then they can optimize for their specific needs, but this results in duplication of effort and reduced productivity
Solution Approach 1:
The patent segments the validation system into independent, reusable components: DUT specification parser, instruction set translator, stimulus generator, and platform interface layer. Each component can be independently developed and reused across different validation scenarios and platforms. This modular architecture allows teams to leverage existing components rather than building complete validation platforms from scratch, significantly improving productivity while maintaining the ability to customize validation for specific needs
Data Source
AI summary
A new approach is proposed to support device under test (DUT) validation reuse across a plurality of platforms, e.g., hardware simulation, hardware emulation, and post-silicon validation. First, an inference profile used for an inference operation of an application, e.g., a machine learning (ML) application, is generated based on a set of profile configurations, a set of test parameters, and a set of randomized constraints. A plurality of math functions specified by, e.g., an architecture team, for the ML application are also statically and/or dynamically verified via block simulation and/or formal verification. An inference model for the DUT is then built based on the inference profile and the plurality of verified math functions. Finally, an inference database including one or more of stimulus, DUT configurations, input data and predicted output results is generated based on the inference model, wherein the inference database for the DUT is reusable across the plurality of platforms.