MLC Data Encoding with Bit Pairing for Balanced Reliability
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Solution Overview
Problem
Existing multi-level cell (MLC) memory systems in convolutional neural networks (CNNs) suffer from unbalanced reliability due to asymmetric error tolerance of bits, where errors in lower error tolerant bits have a significant negative impact on overall system performance, while errors in higher error tolerant bits have a minimal impact.
Innovation Solution
Grouping lower error tolerant bits with higher error tolerant bits in MLC memory arrays and using data scramble techniques to pair error sensitive bits with error insensitive bits, ensuring balanced memory device reliability by storing each bit pair in a 2-bit MLC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lower error tolerant bits are stored separately from higher error tolerant bits, then error sensitivity can be managed, but memory device reliability becomes unbalanced and system performance is significantly impacted when lower error tolerant bits fail
Solution Approach 1:
The patent merges lower error tolerant bits and higher error tolerant bits into the same MLC memory cell. Each MLC stores two bits with opposite error sensitivities (one lower error tolerant bit and one higher error tolerant bit), creating a balanced distribution that prevents catastrophic failure when any single bit fails. This combining approach ensures that no single bit's failure can severely impact system performance.
2Reliability
If data is stored in conventional MLC memory without scrambling, then storage density is achieved, but bit distribution is unbalanced leading to unoptimized reliability
Solution Approach 1:
The patent applies preliminary action by implementing data scrambling techniques before writing data to MLC memory. The input data is scrambled to ensure that lower error tolerant bits and higher error tolerant bits are evenly distributed across all MLC cells before storage. This preliminary scrambling operation optimizes the bit distribution to achieve balanced reliability without requiring complex hardware modifications.
3Productivity
If all bits are treated with equal error tolerance, then simplification is achieved, but the asymmetric impact of bit failures on CNN inference accuracy is not addressed
Solution Approach 1:
The patent applies local quality by recognizing that different bits have different error tolerance characteristics and treating them differently. Lower error tolerant bits (which have greater impact on CNN inference accuracy) are paired with higher error tolerant bits in the same MLC cell. This localized differentiation ensures that bits with higher impact on productivity are given priority protection through balanced pairing, while maintaining overall system efficiency.
Data Source
AI summary
A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.