MLC Memory Trellis Coding for Higher-Density Reliable Storage
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Solution Overview
Problem
Multi-level cell (MLC) memory devices face challenges in improving storage density due to increased reliability issues and read-failure rates as the number of bits stored in a single memory cell increases, limited by the voltage window and decreasing threshold voltage differences between adjacent bits.
Innovation Solution
Implementing Trellis Coded Modulation (TCM) in MLC memory devices, which includes an outer encoder and a TCM modulator to generate program pulses for writing data, and an inner decoder for accurate data reading, using concatenated coding to enhance error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in a single memory cell increases, then storage density is improved, but reliability deteriorates and read-failure rate increases
Solution Approach 1:
The patent changes the parameter of voltage level distribution by introducing TCM modulation with 2m+2 voltage levels instead of the conventional 2m levels. This parameter change allows for better separation between adjacent bit thresholds, maintaining reliability while enabling storage of m bits per cell. The additional voltage levels provide greater margin for error correction and threshold separation.
Solution Approach 2:
The patent employs a composite coding structure combining outer encoder (BCH or LDPC code) with inner TCM encoder. This composite approach integrates two different error correction mechanisms: the outer code handles burst errors and the TCM inner code handles random errors, creating a robust multi-layer error protection system that maintains high reliability at elevated storage densities.
2Quantity of substance
If the number of bits stored in a single memory cell increases, then storage density is improved, but the difference in threshold voltage between adjacent bits decreases
Solution Approach 1:
The patent modifies the voltage level parameter by implementing 2m+2 distinct voltage levels for storing m bits, compared to the standard 2m levels. This creates larger voltage gaps between adjacent bit thresholds, improving the manufacturability and reducing sensitivity to threshold voltage variations. The increased voltage separation directly addresses the decreasing threshold difference problem.
Solution Approach 2:
The patent applies error correction codes (BCH or LDPC outer codes combined with TCM inner codes) that provide beforehand cushioning against threshold voltage variations. The redundant coding structures create a buffer that compensates for manufacturing imprecision, allowing the system to tolerate smaller threshold voltage differences while maintaining data integrity.
3Reliability
If TCM modulation is applied to generate program pulses, then error correction capability is enhanced, but device complexity increases
Solution Approach 1:
The patent segments the error correction function into two distinct parts: an outer encoder that applies BCH or LDPC codes for handling burst errors, and an inner TCM modulator that handles random errors. This segmentation allows each component to be optimized independently and simplifies the overall design by dividing the complex error correction task into manageable modules with clear functional boundaries.
Solution Approach 2:
The TCM modulator acts as an intermediary between the outer encoder and the memory cell array. It transforms the encoded bits into optimized program pulses with 2m+2 voltage levels, providing a buffer that reconciles the digital output of the outer encoder with the analog requirements of the memory cell programming, thereby simplifying the interface between digital logic and analog memory operations.
Data Source
AI summary
A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.