Multi-Level Memory Programming with Two-Phase Verification
Solution Overview
Problem
Conventional flash memory cells face challenges in programming multi-level cells due to wide programming distributions and the second bit effect, which affects neighboring cells through capacitive coupling, leading to inefficiencies and inaccuracies in data storage.
Innovation Solution
A two-phase programming method is introduced, where a preliminary voltage is used for verification and programming, followed by a post-program verify voltage that is different from the preliminary voltage, allowing for more precise control over threshold voltage levels and reducing program disturb and second bit effect impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-phase programming is used, then programming process is simple, but programming distribution is wide and accuracy is poor
Solution Approach 1:
The programming process is divided into two distinct phases: a first programming phase that applies a first voltage to program the memory cell to a first level, and a second programming phase that applies a second voltage to program the memory cell to a second level. This segmentation allows each phase to be optimized independently, achieving narrower programming distributions and higher accuracy without excessive complexity.
Solution Approach 2:
The first programming phase serves as a preliminary action that prepares the memory cell by programming it to an intermediate level. This preliminary programming reduces the second bit effect and narrows the distribution before the final programming phase, improving overall accuracy.
2Productivity
If higher programming voltage is applied to achieve faster programming, then programming speed increases, but program disturb to neighboring cells increases
Solution Approach 1:
Different voltages are applied to different cells based on their programming status. The method applies a first voltage to cells being programmed to the first level and a second voltage to cells being programmed to the second level, allowing optimized voltage application that reduces program disturb to neighboring cells while maintaining programming speed.
Solution Approach 2:
The first programming phase with the first voltage serves as a preliminary action that reduces the second bit effect before the second programming phase. This preliminary programming at a controlled voltage level prevents excessive voltage stress on neighboring cells, reducing program disturb.
3Manufacturing precision
If incremental stepping of drain line voltage is used to reduce second bit effect, then programming accuracy improves, but programming time increases
Solution Approach 1:
The programming process is segmented into two phases with distinct voltage applications. The first phase programs to an intermediate level with controlled voltage steps, and the second phase completes the programming to the final level. This segmentation achieves accurate threshold voltage control without requiring excessive incremental steps, reducing programming time.
Solution Approach 2:
The first programming phase acts as a preliminary action that establishes an intermediate threshold voltage level, reducing the second bit effect before the second phase. This preliminary action narrows the distribution early in the process, allowing faster convergence to the final level.
4Manufacturing precision
If verification voltage is the same as programming voltage, then verification process is simple, but programming distribution remains wide
Solution Approach 1:
The verification process is segmented into two corresponding phases: a first verification phase that verifies programming to the first level using a first voltage, and a second verification phase that verifies programming to the second level using a second voltage. This segmented verification approach narrows the programming distribution by providing targeted verification at each stage without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in narrower threshold voltage distributions and wider read windows, improving programming accuracy and reducing program time by using a learned bit line value that is less likely to be too low, thereby enhancing the programmability of multi-level cell arrays.
Implementation Method 1
Another type of memory uses a charge-trapping structure rather than a conductive gate material used in floating gate devices. When a charge-trapping layer is programmed, the charge may be trapped so that it does not move through the non-conductive layer. The charge may therefore be retained by the charge-trapping layer until the memory cell is erased
Implementation Method 2
A particular bit can typically be programmed, for example, by applying a potential to the gate 14 with one of the S/D regions 16 and 18 (e.g., region 18) acting as a drain and the other of the S/D regions 16 and 18 (e.g., region 20) acting as the source. The accumulation of charge at the particular side alters the threshold voltage of the left storage side 22 or right storage side 24.
Data Source
AI summary
A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV1′), programming the first memory cell targeted to the first level in the first program phase, and verifying the first memory cell with a first post program-verify voltage of the first program phase (PV1′) in which the first post program-verify voltage is different from the first preliminary voltage. A corresponding apparatus is also provided.