Multilayer Ceramic Capacitor Asymmetric Electrode Noise Reduction
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Solution Overview
Problem
Multilayer ceramic capacitors generate significant acoustic noise due to piezoelectric vibrations, which is discomforting, and existing methods to reduce noise increase equivalent series inductance (ESL), deteriorating high-frequency properties.
Innovation Solution
A multilayer ceramic capacitor design with a ceramic body ratio of length to width between 1.39 and 2.12 and external electrode length to thickness ratio between 8.05 and 10.56, along with a manufacturing method that forms external electrodes to connect internal electrodes, effectively reduces acoustic noise and ESL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the length of external electrode is made smaller than length or width of ceramic body to decrease acoustic noise, then acoustic noise is reduced, but equivalent series inductance (ESL) is increased
Solution Approach 1:
The patent applies asymmetry by making the external electrode length (B) smaller than the ceramic body length (L), creating an asymmetric configuration where B < L. This asymmetric design reduces the vibration transmission area to acoustic noise while maintaining electrical connectivity through optimized electrode positioning and sizing.
Solution Approach 2:
The patent changes geometric parameters by defining specific ratio relationships: L/W between 1.39-2.12 and B/Cv between 8.05-10.56. These parameter optimizations allow the external electrode to be shorter than the ceramic body (reducing noise) while maintaining appropriate ESL through controlled dimensional relationships.
2Reliability
If equivalent series inductance (ESL) of multilayer ceramic capacitor is increased, then high frequency properties are deteriorated, but acoustic noise reduction becomes insufficient
Solution Approach 1:
The patent optimizes geometric parameters (L/W ratio and B/Cv ratio) to achieve a balance where the external electrode is shortened for noise reduction while maintaining ESL within acceptable ranges through controlled dimensional relationships, preventing deterioration of high-frequency properties.
Solution Approach 2:
The patent applies local quality by optimizing specific regions: the external electrode length (B) is locally reduced compared to the ceramic body length (L) to decrease noise, while the width (W) and thickness (Cv) are maintained or optimized to preserve electrical performance and high-frequency characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly decreases acoustic noise and suppresses ESL, maintaining high-frequency properties, thereby effectively reducing noise and ripple voltage when mounted on a circuit board.
Implementation Method 1
since the dielectric layers have piezoelectric properties, when a direct current (DC) voltage or an alternating current (AC) voltage is applied to the multilayer ceramic capacitor, a piezoelectric phenomenon may be generated between the internal electrodes, such that a volume of a ceramic body is expanded and contracted according to a frequency, thereby generating periodic vibrations
Data Source
AI summary
There is provided a multilayer ceramic capacitor including, a ceramic body including a plurality of dielectric layers, a plurality of first and second internal electrodes disposed in the ceramic body to be alternately exposed through the double side surfaces facing each other in a width direction, having the dielectric layers therebetween, and first and second external electrodes formed on the surfaces of the ceramic body in the width and thickness directions and electrically connected to the first and second internal electrodes, wherein when a length of the ceramic body is defined as L and a width of the ceramic body is defined as W, a ratio L/W of the length L to the width W of the ceramic body satisfies 1.39≦L/W≦2.12.