MLCC Ceramic Interlayer for Sintering Stress and Electrode Integrity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Multilayer ceramic capacitors (MLCCs) face issues of stress non-uniformity and disconnection between dielectric and internal electrodes due to differing shrinkage rates during sintering, leading to reduced capacitance and degraded insulation resistance.

Innovation Solution

Incorporating a ceramic layer between the dielectric and internal electrodes, with a controlled pore area ratio, to suppress stress non-uniformity and enhance connectivity, using methods like sputtering or ALD to form the ceramic layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional MLCC structure without a ceramic layer is used, then the device complexity is low, but stress non-uniformity occurs between the dielectric layer and internal electrode during sintering, leading to disconnection and agglomeration of internal electrodes

Engineering Contradiction:
ImprovereliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A ceramic layer is introduced as an intermediary between the dielectric layer and the internal electrode. This ceramic layer acts as a buffer that mediates the stress non-uniformity during sintering, preventing direct stress concentration at the dielectric-electrode interface. The ceramic layer has different mechanical properties from both the dielectric and the electrode, allowing it to absorb and distribute stress uniformly, thereby preventing disconnection and agglomeration of internal electrodes while improving overall reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the internal electrode thickness is increased to prevent disconnection, then the reliability improves, but the capacitance per unit volume is reduced

Engineering Contradiction:
ImprovereliabilityVSAvoidcapacitance per unit volume
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The ceramic layer serves as a protective intermediary that allows the internal electrode to maintain optimal thickness without disconnection. By distributing stress uniformly during sintering, the ceramic layer enables the use of thinner internal electrodes that would otherwise be prone to disconnection, thereby maximizing the dielectric layer thickness and capacitance per unit volume while maintaining reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The introduction of the ceramic layer changes the stress distribution parameters during sintering. This parameter change allows for optimization of the internal electrode thickness parameter, enabling thinner electrodes to be used without sacrificing reliability, thus improving capacitance per unit volume.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If the dielectric layer thickness is reduced to increase capacitance per unit volume, then the capacitance per unit volume improves, but stress non-uniformity and disconnection of internal electrodes worsen

Engineering Contradiction:
Improvecapacitance per unit volumeVSAvoidreliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The ceramic layer acts as a stress-distributing intermediary that compensates for the reduced dielectric layer thickness. By providing a buffer zone between the dielectric and the internal electrode, the ceramic layer ensures uniform stress distribution even when the dielectric layer is thin, preventing stress concentration and internal electrode disconnection, thereby enabling high capacitance per unit volume while maintaining reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Stress or pressure

If a ceramic layer with high pore content is used, then the stress non-uniformity is reduced, but the insulation resistance deteriorates

Engineering Contradiction:
Improvestress non-uniformityVSAvoidinsulation resistance
Core Design Contradiction:
Stress or pressureVSReliability

Solution Approach 1:

The pore area ratio of the ceramic layer is precisely controlled within the range of 0.01 to 0.05. This parameter optimization achieves a balance between stress distribution and insulation performance. The controlled porosity provides sufficient stress buffering capacity while maintaining adequate insulation resistance, preventing both disconnection and insulation degradation.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The ceramic layer is designed with specific local properties - a controlled pore area ratio that provides stress distribution functionality while maintaining insulation. The porosity is localized to the ceramic layer rather than the entire structure, allowing stress management in the critical interface region without compromising the overall insulation resistance of the device.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves capacitance per unit volume and reliability by minimizing stress non-uniformity and disconnection, allowing for smaller and higher-capacitance MLCCs.

Implementation Method 1

During a sintering process, a difference in shrinkage rates between the dielectric layer and the internal electrode may occur. Due to such a difference in shrinkage rates, stress non-uniformity may occur between the dielectric layer and the internal electrode

Methodology Applied
Scientific EffectSintering: Sintering

Implementation Method 2

When an area ratio occupied by pores with respect to the ceramic layer is Sp1 and an area ratio occupied by pores with respect to the dielectric layer is Sp2, Sp1 may be less than 5%

Methodology Applied
Scientific EffectPorosity: Porosity

Data Source

PatentUS12482603B2Multilayer electronic component and method of manufacturing multilayer electronic component
Publication Date: 2025.11.25 SAMSUNG ELECTRO MECHANICS CO LTD
  • US12482603B2 patent drawing
  • US12482603B2 patent drawing
  • US12482603B2 patent drawing

AI summary

A multilayer electronic component includes a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer, and an external electrode disposed on the body. A ceramic layer is disposed between the dielectric layer and the internal electrode. When an area ratio occupied by pores with respect to the ceramic layer is Sp1 and an area ratio occupied by pores with respect to the dielectric layer is Sp2, Sp1 is less than 5%, and Sp1<Sp2 is satisfied.