Multilayer Ceramic Capacitor Dimensional Optimization for Reduced Substrate Mounting
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Solution Overview
Problem
The challenge is to efficiently mount multilayer ceramic capacitors on reduced-size mounting substrates due to size mismatches between the capacitors and the substrates, which affects their effective utilization in electronic apparatuses.
Innovation Solution
The design involves a multilayer ceramic capacitor with specific dimensions and structural features, including laminated dielectric and inner electrode layers, external electrodes, and optimized dimensions for edge and side surfaces, allowing efficient mounting on substrates with perpendicular edge portions, ensuring reliable and high-capacity performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multilayer ceramic capacitors with normalized sizes are used, then manufacturing and handling are simplified, but mounting efficiency on reduced-size substrates deteriorates due to size mismatch
Solution Approach 1:
The patent applies parameter changes by providing multilayer ceramic capacitors with specific non-normalized dimensions (0.4mm×0.2mm×0.2mm, 0.6mm×0.3mm×0.3mm, or 1.0mm×0.5mm×0.5mm) that are optimized for mounting on reduced-size substrates. This dimensional parameter adjustment allows the capacitors to fit efficiently on substrates with minimized mounting areas while maintaining manufacturability
Solution Approach 2:
The patent enables dynamic adaptability by offering multiple size specifications that can be selected based on the specific mounting substrate requirements. This allows the capacitor dimensions to be dynamically matched to different substrate sizes, optimizing mounting efficiency for various electronic apparatus configurations
2Volume of moving object
If the mounting substrate size is reduced, then the overall electronic apparatus size is minimized, but the mounting area for capacitors is minimized causing size mismatch
Solution Approach 1:
The patent resolves the area mismatch by providing capacitors with specifically optimized dimensions that match the reduced mounting areas. The capacitor sizes (0.4mm×0.2mm, 0.6mm×0.3mm, or 1.0mm×0.5mm in length×width) are parameter-adjusted to fit efficiently on minimized substrate mounting areas while maintaining functional performance
Solution Approach 2:
The patent utilizes dimensional optimization by carefully selecting length, width, and height parameters of the capacitors to maximize space utilization on the reduced substrate. The height dimension (0.2mm, 0.3mm, or 0.5mm) is optimized to provide sufficient capacitance while minimizing the footprint area on the substrate
Data Source
AI summary
An electronic component is able to be mounted on a mounting substrate including a pair of first edge portions that faces each other, and a pair of second edge portions that is perpendicular or substantially perpendicular to the pair of first edge portions and faces each other. The mounting substrate has a structure that allows at least any one of the electronic component, a first electronic component, and a second electronic component, to be mounted thereon. When a dimension of the first electronic component in a length direction is designated as L1, a dimension of the first electronic component in a width direction is designated as W1, a dimension of the second electronic component in the length direction is designated as L2, and a dimension of the second electronic component in the width direction is designated as W2, a dimension of the electronic component in the width direction is any one of W1 and W2. A dimension of the electronic component in the length direction is L2 when the dimension of the electronic component in the width direction is W1, and is L1 when the dimension of the electronic component in the width direction is W2.