3-Terminal Multilayer Ceramic Capacitor ESL Reduction
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Solution Overview
Problem
The increasing demand for miniaturized and high-capacitance electronic components, particularly multilayer ceramic capacitors, is hindered by elevated equivalent series inductance (ESL) which degrades performance, especially in integrated circuits where decoupling capacitors are used, necessitating a solution to reduce inductance and enhance low ESL characteristics.
Innovation Solution
A multilayer ceramic capacitor design with three external electrodes spaced apart on a ceramic body, where the length to width ratio (A/L) of the active region is between 0.64 and 1.14, effectively minimizing the current flow path and reducing ESL, while maintaining high capacitance and preventing manufacturing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the multilayer ceramic capacitor is miniaturized and designed for high capacitance, then the capacitance density increases, but the equivalent series inductance (ESL) increases causing performance deterioration
Solution Approach 1:
The patent transitions from a conventional 2-terminal planar structure to a 3-terminal vertical structure where external electrodes are arranged in a triangular pattern on the mounting surface. This dimensional reconfiguration shortens the current flow path by utilizing the vertical stacking of internal electrodes and optimizing their projection positions, thereby reducing ESL while maintaining high capacitance in miniaturized packages
Solution Approach 2:
The patent optimizes geometric parameters including the ratio of active region width to ceramic body length (A/L between 0.64-1.14), the triangular arrangement of external electrodes, and the vertical stacking configuration of internal electrodes. These parameter changes minimize the current loop area and reduce equivalent series inductance while achieving high capacitance density in small form factors
2Object-affected harmful factors
If the distance between external terminals is reduced to decrease current flow path, then inductance decreases improving performance, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs an asymmetric triangular arrangement of three external electrodes on the mounting surface rather than a symmetric pattern. This asymmetric configuration optimizes the current flow path geometry to minimize inductance while providing sufficient spacing between electrodes that accommodates manufacturing tolerances and prevents short circuits during assembly
Solution Approach 2:
By utilizing the vertical dimension through stacked internal electrodes and their strategic projection positions, the patent achieves short current paths without requiring extremely small horizontal distances between external terminals. This dimensional approach reduces inductance while maintaining manufacturable electrode spacing
Data Source
AI summary
A multilayer ceramic capacitor may include three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from one another. When a length of the ceramic body is defined as L, and a width of an active region including a plurality of internal electrodes disposed therein in a width direction of the ceramic body is defined as A, A/L is in a range of 0.64 to 1.14 (0.64≤A/L≤1.14).