Multilayer Ceramic Capacitor ESL Reduction via Three-Terminal Vertical Design
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Solution Overview
Problem
Multilayer ceramic capacitors face performance deterioration due to increased equivalent series inductance (ESL), which is exacerbated by miniaturization and higher capacitance demands, particularly in integrated circuits, necessitating a reduction in ESL to maintain effective performance.
Innovation Solution
A multilayer ceramic capacitor design with three external electrodes spaced apart on a ceramic body, where the thickness of the active layer and the gap between lead parts are optimized to satisfy the equation 0.00044≤LG*log [1/AT]≤0.00150, reducing ESL to 50 pH or less by minimizing the current flow path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the multilayer ceramic capacitor is miniaturized and capacitance is increased, then the size is reduced and capacitance is increased, but the equivalent series inductance increases and performance deteriorates
Solution Approach 1:
The patent transitions from a conventional two-terminal planar structure to a three-terminal vertical multilayer structure. By stacking internal electrodes vertically and bringing external terminals closer together in the vertical dimension, the current loop area is reduced, thereby decreasing equivalent series inductance (ESL) to 50 pH or less while maintaining miniaturization and high capacitance requirements
Solution Approach 2:
The patent optimizes specific geometric parameters including the thickness of the active layer (AT) and the gap between lead parts (LG) to satisfy the equation 0.00044≤LG*log[1/AT]≤0.00150. This parameter optimization minimizes the current flow path length and loop area, achieving low ESL characteristics while maintaining the required size and capacitance specifications
2Reliability
If the distance between external terminals is increased, then the current flow path is reduced and inductance is decreased, but the device size increases
Solution Approach 1:
Instead of increasing terminal distance in the horizontal plane (which would increase device footprint), the patent utilizes the vertical dimension by stacking multiple internal electrode layers. This three-terminal vertical configuration shortens the current loop path in the vertical direction while maintaining a compact horizontal footprint, achieving low inductance without increasing overall device size
3Reliability
If the gap between lead parts is reduced, then the current loop area is minimized and ESL is decreased, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes a specific mathematical relationship 0.00044≤LG*log[1/AT]≤0.00150 between the gap (LG) and active layer thickness (AT) parameters. This equation provides a design guideline that balances ESL reduction with manufacturability, allowing optimization of low ESL characteristics while maintaining reasonable manufacturing precision requirements through coordinated control of multiple parameters rather than extreme single-parameter optimization
Data Source
AI summary
A multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from one another. When a thickness of an active layer including a plurality of first and second internal electrodes disposed therein is defined as AT, and a gap between a first or second lead part of the first internal electrode and a third lead part of the second internal electrode is defined as LG, the following Equation may be satisfied: 0.00044≤LG*log [1/AT]≤0.00150.