MLCC Side Margin Grain Structure for Moisture Resistance
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Solution Overview
Problem
The miniaturization of multilayer ceramic capacitors for high-capacitance applications leads to reliability issues due to the generation of pores at the interface between the ceramic body and the side margin portions, affecting moisture resistance and sintering compactness.
Innovation Solution
A multilayer ceramic capacitor design with side margin portions having distinct regions of different dielectric grain sizes and magnesium content, where the second region adjacent to the internal electrodes has larger grains and higher magnesium content, reducing pore density and improving moisture resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If internal electrodes are exposed in the width direction to maximize electrode area, then capacitance is improved, but pores are generated at the interface with side margin portions
Solution Approach 1:
The patent applies local quality by creating distinct regions within the side margin portion with different dielectric grain sizes. The first region has smaller grains while the second region has larger grains, allowing each region to serve different functions: the first region provides structural integrity while the second region reduces pore formation at the electrode interface, thus maintaining both high capacitance and reliability.
Solution Approach 2:
The patent uses composite materials by combining dielectric layers with different grain size characteristics within the side margin portion. This composite structure integrates materials with small grains (for mechanical strength) and large grains (for reduced porosity and improved moisture resistance), resolving the contradiction between maximizing electrode exposure and preventing pore generation.
2Area of stationary object
If side margin portion is attached in pre-sintering operation, then electrode area is maximized, but sintering compactness deteriorates due to pores
Solution Approach 1:
The patent implements local quality by differentiating dielectric grain sizes in different regions of the side margin portion. The second region with larger grains specifically addresses sintering compactness at the electrode interface, while the first region with smaller grains maintains overall structural integrity, thus achieving both maximum electrode area and high sintering compactness.
Solution Approach 2:
The patent applies parameter changes by varying the dielectric grain size parameter within the side margin portion. By controlling grain size to be larger in the second region adjacent to internal electrodes and smaller in the first region, the patent optimizes both electrode area exposure and sintering compactness, preventing pore formation while maximizing capacitance.
Data Source
AI summary
A multilayer ceramic capacitor includes a ceramic body including dielectric layers, a plurality of internal electrodes disposed in the ceramic body, and a first side margin portion and a second side margin portion respectively arranged on end portions of the internal electrodes exposed to first and second surfaces. The first and second side margin portions each include a first region adjacent to an outward facing side surface of the respective side margin portion, and a second region adjacent to the internal electrodes exposed to the first and second surfaces of the ceramic body, and an average size of dielectric grains included in the second region is larger than an average size of dielectric grains included in the first region.