Coreless mm-Wave Antenna Package With Asymmetric Build-Up Layers
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Solution Overview
Problem
Current semiconductor packages with millimeter-wave antennas face challenges such as high costs due to expensive cored substrates, reduced antenna efficiency from solid ground planes, and substrate warpage issues during fabrication and testing.
Innovation Solution
The implementation of an asymmetric build-up layer count on a temporary substrate and the incorporation of dummification elements near antenna elements to reduce layer count, enhance antenna gain and efficiency, and provide mechanical robustness, while also minimizing surface current and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If cored substrates are used in semiconductor packages, then antenna bandwidth is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive cored substrates with a temporary substrate that is removed after fabrication. The build-up layers are formed on this temporary substrate, then the substrate is stripped away, leaving the antenna structure without requiring costly cored substrate materials throughout the package.
Solution Approach 2:
The patent changes the physical state and presence of the substrate by using a temporary substrate that is later removed. This transforms the substrate from a permanent structural component to a temporary fabrication aid, enabling cost reduction while maintaining antenna performance through controlled layer removal.
2Reliability
If solid ground planes are implemented, then electrical shielding is improved, but antenna efficiency decreases due to surface current
Solution Approach 1:
The patent applies different ground plane configurations to different regions. Solid ground planes are used in areas where electrical shielding is critical, while regions near antenna elements use reduced or patterned ground planes to minimize surface current and maintain antenna efficiency. This localized differentiation resolves the contradiction between shielding and efficiency.
Solution Approach 2:
Instead of implementing solid ground planes across the entire package, the patent uses partial ground planes only where necessary for electrical shielding. This partial action provides sufficient shielding protection while avoiding the harmful surface current effects that would occur with complete ground plane coverage near antenna elements.
3Device complexity
If symmetric build-up layers are used, then manufacturing process is simplified, but substrate warpage occurs during fabrication and testing
Solution Approach 1:
The patent deliberately uses asymmetric build-up layer configurations on the temporary substrate. Different numbers and thicknesses of build-up layers are applied to different sides to compensate for expected warpage during fabrication and testing. This asymmetric design pre-balances the structure to maintain flatness throughout the manufacturing process.
Solution Approach 2:
The asymmetric build-up layers are designed in advance to counteract the warpage that will occur during subsequent fabrication and testing steps. By pre-applying compensating stresses through asymmetric layering, the patent prevents warpage issues before they manifest, ensuring substrate stability throughout manufacturing.
4Ease of manufacture
If layer count is reduced, then manufacturing cost decreases, but antenna gain and efficiency may be compromised
Solution Approach 1:
The temporary substrate enables reduced layer count by allowing layers to be formed and then selectively removed. This disposable substrate approach eliminates the need for permanent structural layers that would otherwise be required for support, reducing overall layer count and cost while maintaining antenna performance through precise layer control.
Solution Approach 2:
The patent optimizes the thickness and material properties of remaining layers after substrate removal to compensate for reduced layer count. By carefully controlling the parameters of the retained build-up layers, the patent maintains adequate mechanical support and electrical performance with fewer total layers, achieving cost reduction without sacrificing antenna gain.
Data Source
AI summary
In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.