Mobile DDR Clock Scheme with Local Frequency Multiplication
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Solution Overview
Problem
Mobile DDR memory's high-speed clock scheme circuits consume excessive power, necessitating a low-power design for efficient operation in mobile electronic devices.
Innovation Solution
A clock scheme circuit with a global clock generator and a local clock generator using a frequency multiplier, such as a multiplying delay-locked loop (MDLL), delay-locked loop (DLL), or phase-looked loop (PLL), to generate a high-frequency local clock signal from a low-frequency global clock signal, reducing power consumption along the global clock trace.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed clock scheme circuit is used in mobile DDR memory, then the data transmission speed is improved, but the power consumption increases excessively
Solution Approach 1:
The clock circuit is segmented into global clock generator, global clock trace, and local clock generator with frequency multiplier. The global clock trace operates at low frequency to minimize power consumption, while the local clock generator multiplies the frequency locally to achieve high-speed data transmission without requiring the entire clock distribution network to operate at high frequency.
Solution Approach 2:
The frequency multiplier is placed locally at the memory core to generate high-frequency clock signals only where needed for high-speed data transmission. The global clock distribution network maintains low frequency to reduce power consumption along the clock traces, achieving local high performance without global power overhead.
2Speed
If the global clock signal operates at high frequency to support high-speed data transmission, then the data transmission speed is improved, but the power consumption along the global clock trace increases
Solution Approach 1:
The clock signal generation is segmented such that the global clock trace carries only low-frequency reference signals, while frequency multiplication is performed locally at the destination. This segmentation allows the global distribution network to operate efficiently at low power while still supporting high-speed local operations.
Solution Approach 2:
The frequency parameter of the clock signal is changed along the signal path: the global clock generator produces a low-frequency reference signal for efficient distribution, and the local frequency multiplier changes this parameter to high frequency only where needed for high-speed data transmission.
Data Source
AI summary
A clock scheme circuit with low power consumption is shown. A local clock generator is coupled to a global clock generator through a global clock trace to receive a global clock signal, and generate a local clock signal based on the global clock signal. The local clock generator uses a frequency multiplier to multiply the frequency of the global clock signal by a multiplication factor of not less than 1. Thus, the global clock signal transferred through the global clock trace can be a lower-frequency signal in comparison with the local clock signal. The power consumption along the global clock trace is considerably reduced.