Modeling Dielectric Coating of Conductor Using Displacement Current
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Solution Overview
Problem
Conventional 3D electromagnetic modeling simulators face excessive computational and storage requirements due to large aspect ratio differences in thin dielectric coating layers, limiting their application to structures with geometrical complexity, and fail to accurately model finite dielectric layers and voltage-dependent MOS effects.
Innovation Solution
A method involving meshing a conductor's surface into multiple cells, modeling displacement currents through the substrate and dielectric coating, and incorporating capacitance effects to represent the dielectric layer's capacitive impact, using a 3D planar electromagnetic simulator that extends the application range to include TSV connections and other components with dielectric coatings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional 3D EM simulators use volume discretization techniques (FEM or FDTD) to model conductor structures with thin dielectric coating layers, then the electromagnetic effects are captured, but the number of mesh elements becomes prohibitively large due to large aspect ratio differences, exceeding processing and storage capacity
Solution Approach 1:
The patent segments the dielectric coating into two distinct parts: (1) a thin coating layer adjacent to the conductor surface, and (2) a thicker substrate layer extending to the ground plane. This segmentation allows different modeling approaches to be applied to each part - the thin coating is handled through surface impedance boundary conditions while the substrate is modeled using volume discretization, thereby reducing the total number of mesh elements required while maintaining electromagnetic modeling accuracy.
Solution Approach 2:
The patent transitions from a purely volumetric 3D discretization approach to a hybrid approach that incorporates surface-based modeling for the thin dielectric coating. By using surface impedance boundary conditions on the conductor-dielectric interface, the model effectively reduces the dimensionality of the discretization problem in the region of the thin coating, avoiding the need to create extremely fine volumetric mesh elements in that region.
2Measurement precision
If 3D EM simulators use surface discretization techniques (BEM) to model dielectric coatings, then the electromagnetic boundary effects are captured, but the size of the discretized problem dramatically increases, exceeding processing and storage capacity
Solution Approach 1:
The patent segments the dielectric structure into a thin coating layer and a thicker substrate layer, applying different discretization strategies to each. The thin coating layer is modeled using surface impedance boundary conditions that capture boundary electromagnetic effects without requiring full surface discretization, while the substrate layer uses volume discretization. This segmentation reduces the overall size of the discretized problem while maintaining accuracy in capturing boundary effects.
3Productivity
If 3D planar EM simulators use Green's function technology to model dielectric layers, then the simulation speed is improved without additional discretization cost, but the technology only supports planar dielectric layers extending to infinity and cannot handle finite 3D dielectric layers and coatings
Solution Approach 1:
The patent segments the dielectric structure into a thin coating layer (modeled with surface impedance boundary conditions suitable for finite geometries) and a substrate layer (modeled with volume discretization). This segmentation allows the model to handle finite 3D dielectric structures rather than requiring infinite planar layers, while still maintaining computational efficiency by avoiding full volumetric discretization of the thin coating region.
Solution Approach 2:
The patent applies different modeling approaches to different regions of the dielectric structure based on their local characteristics. The thin coating layer adjacent to the conductor surface, where the aspect ratio problem exists, is modeled using surface impedance boundary conditions. The thicker substrate layer, where volumetric effects are more significant, is modeled using volume discretization. This local quality approach allows the model to handle finite 3D geometries efficiently.
4Productivity
If application focused solutions like TSV modeling use global cylindrical basis functions instead of meshing, then rapid modeling is achieved with fewer unknowns, but the geometry specifics of TSV structures are embedded and flexibility to apply to more general structures is lost
Solution Approach 1:
The patent develops a universal modeling approach that can handle various conductor-dielectric configurations (including but not limited to TSV structures) by using surface impedance boundary conditions combined with volume discretization. This universal method maintains the computational efficiency of basis function approaches while preserving the geometry flexibility of mesh-based methods, allowing application to general 3D structures with finite dielectric layers and coatings.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces computational costs, enhances model flexibility, and accurately captures electromagnetic effects, including voltage-dependent MOS effects, without exceeding processing and storage capacity, enabling more complex structure simulations.
Implementation Method 1
Modeling the second displacement current includes determining a coating capacitance connected in series between the node corresponding to each conductor cell and the first branch, the coating capacitance representing a capacitive effect of the dielectric layer
Data Source
AI summary
A method for modeling a conductor in a substrate and a dielectric coating formed between the conductor and the substrate includes meshing a surface of the conductor into multiple conductor cells, each cell including a corresponding node in network topology, modeling a first displacement current flowing from each cell through the substrate, and modeling a second displacement current flowing from each cell through the dielectric coating. Modeling the first displacement current includes determining a first branch connecting the node corresponding to each conductor cell to ground, the first branch having at least a first capacitance. Modeling the second displacement current includes determining a coating capacitance connected in series between the node corresponding to each conductor cell and the first branch, the coating capacitance representing a capacitive effect of the dielectric layer.