Modified Internal Clearance for Press-Fit Connector Apertures
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Solution Overview
Problem
Press-fit connectors in multilayer circuit board assemblies face challenges with deformation causing potential laminate cracking and reduced dielectric spacing between conductors, leading to reliability issues and increased risk of electrical shorting.
Innovation Solution
A method of fabricating multilayer circuit boards with modified voltage-to-ground clearance regions around apertures, oriented based on the configuration and orientation of connector pins, to enhance clearance between conductive materials and mitigate deformation-induced risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If press-fit connectors are inserted into apertures of multilayer circuit boards, then connector connection is achieved, but deformation occurs causing laminate cracking and reduced dielectric spacing between conductors
Solution Approach 1:
The patent applies preliminary action by pre-defining modified internal clearance regions around apertures before connector insertion. These clearance regions are designed with enlarged dimensions in the direction of greatest normal force to accommodate expected deformation from press-fit connector insertion, thereby maintaining sufficient dielectric spacing between conductors even after deformation occurs.
Solution Approach 2:
The patent applies local quality by modifying the internal clearance regions specifically around apertures where press-fit connectors will be inserted, rather than uniformly increasing clearances throughout the entire circuit board. The modification is localized to areas experiencing greatest normal force during connector insertion, preserving dielectric spacing only where needed while maintaining overall board compactness.
2Ease of operation
If connector pins are press-fit connected into apertures, then component coupling is achieved, but deformation causes potential electrical shorting between conductors
Solution Approach 1:
The patent applies preliminary action by pre-defining modified internal clearance regions around apertures before connector insertion. These clearance regions are designed with enlarged dimensions in the direction of greatest normal force to accommodate expected deformation from press-fit connector insertion, thereby maintaining sufficient dielectric spacing between conductors even after deformation occurs.
Solution Approach 2:
The patent applies preliminary anti-action by designing the modified internal clearance regions to counteract the harmful effect of deformation-induced conductor proximity. The enlarged clearance regions are positioned and dimensioned to prevent electrical shorting between conductors that would otherwise be at risk due to deformation from connector insertion.
3Ease of manufacture
If standard internal clearance regions are used around apertures, then manufacturing simplicity is maintained, but sufficient dielectric spacing cannot be ensured after connector insertion deformation
Solution Approach 1:
The patent applies preliminary action by pre-defining modified internal clearance regions around apertures before connector insertion. These clearance regions are designed with enlarged dimensions in the direction of greatest normal force to accommodate expected deformation from press-fit connector insertion, thereby maintaining sufficient dielectric spacing between conductors even after deformation occurs.
Solution Approach 2:
The patent applies parameter changes by modifying the dimensions of internal clearance regions around apertures. Specifically, the clearance regions are enlarged in the direction of greatest normal force during connector insertion, changing the geometric parameters of the clearance to ensure sufficient dielectric spacing is maintained after deformation.
Data Source
AI summary
A method of fabricating a multilayer circuit board is provided which includes forming a layer of a the multilayer circuit board with an internal clearance region having a modified voltage-to-ground clearance of conductive material adjacent to an aperture of the multilayer circuit board. The modified voltage-to-ground clearance of conductive material is based on a configuration of a connector pin to be press-fit connected within the aperture of the multilayer circuit board, and the internal clearance region is enlarged in a direction of greatest normal force outward from the aperture with insertion of the connector pin into the aperture.


